from ReBba.Components.ShiftRegister import ShiftRegister
from ReBba.Components.ExiClock import ClockState

from amaranth import Const, Elaboratable, Module, Signal
from amaranth.build import Platform


class ExiRequest(Elaboratable):
    
    def __init__(self):
        #ports
        self.request = Signal(16)
        self.nen = Signal(1)
        self.rst = Signal(1)
        self.exiClkState = Signal(2)
        self.exiIn = Signal(1)
        self.requestComplete = Signal(1)

        #state
        self.disableShift = Signal(1, reset=0)
        self.shiftRegister = ShiftRegister(16)
        self.clockCount = Signal(5, reset=0)

    def elaborate(self, platform: Platform):
        m = Module()

        m.submodules += self.shiftRegister

        m.d.comb += self.request.eq(self.shiftRegister.data)
        m.d.comb += self.shiftRegister.inb.eq(self.exiIn)
        m.d.comb += self.shiftRegister.exiClkState.eq(self.exiClkState)
        m.d.comb += self.shiftRegister.nen.eq(self.disableShift)

        with m.If(~self.nen):
            with m.If(self.clockCount != 16):
                with m.If(self.exiClkState == ClockState.FALLING):
                    m.d.sync += self.clockCount.eq(self.clockCount + 1)
                
            with m.If(self.clockCount == 16):
                m.d.comb += self.disableShift.eq(Const(1))
                m.d.comb += self.requestComplete.eq(Const(1))

        with m.If(self.rst):
            m.d.comb += self.request.eq(self.request.reset)
            m.d.sync += self.clockCount.eq(self.clockCount.reset)
            m.d.comb += self.disableShift.eq(self.disableShift.reset)

        m.d.comb += self.shiftRegister.rst.eq(self.rst)

        return m