import sys
import os
from amaranth import *
from amaranth.back import verilog
from amaranth.build.plat import Platform
from amaranth.sim import Simulator
from amaranth_boards.icebreaker import *

from ExiClock import ExiClock
from ExiRequest import ExiRequest
from Debouncer import Debouncer
from ExiDecoder import ExiDecoder

class ReBba(Elaboratable):
    def __init__(self):
        pass

    def elaborate(self, platform: Platform):
        m = Module()

        uledg = platform.request("led_g", 0)
        uledr = platform.request("led_r", 0)

        led1 = platform.request("led_g", 1)
        led2 = platform.request("led_g", 4)
        led3 = platform.request("led_g", 2)
        led4 = platform.request("led_g", 3)
        led5 = platform.request("led_r", 1)

        btn1 = platform.request("button", 1)
        btn2 = platform.request("button", 2)
        btn3 = platform.request("button", 3)

        debounce1 = Debouncer(10000)
        m.submodules += debounce1

        m.d.comb += debounce1.input.eq(btn3)

        exiClk = ExiClock()
        m.submodules += exiClk
        
        m.d.comb += exiClk.exiClk.eq(debounce1.output)
        
        exiReq = ExiRequest()
        m.submodules += exiReq

        m.d.comb += exiReq.exiClkState.eq(exiClk.exiClkState)
        m.d.comb += exiReq.exiIn.eq(btn1)
        m.d.comb += exiReq.rst.eq(btn2)

        m.d.comb += led1.eq(exiReq.request[0])
        m.d.comb += led2.eq(exiReq.request[1])
        m.d.comb += led3.eq(exiReq.request[2])
        m.d.comb += led4.eq(exiReq.request[3])

        m.d.comb += led5.eq(exiReq.requestComplete)

        exiDec = ExiDecoder()
        m.submodules += exiDec

        m.d.comb += exiDec.request.eq(exiReq.request)
        m.d.comb += uledr.eq(exiDec.request_type[0])
        m.d.comb += uledg.eq(exiReq.requestComplete)

        return m

class TestBench:
    def __init__(self):
        pass

    def simulate(self):
        pass

def main():
    if(len(sys.argv) == 2):

        if sys.argv[1] == "s":
            bench = TestBench()
            bench.simulate()
        
        if sys.argv[1] == "v":
            mod = ReBba()
            with open(os.path.dirname(os.path.abspath(__file__)) + "/bba.v", "w") as f:
                f.write(verilog.convert(mod, ports=[]))

        if sys.argv[1] == "p":
            mod = ReBba()
            platform = ICEBreakerPlatform()
            platform.add_resources(platform.break_off_pmod)
            platform.build(mod, do_program=True)
    
    else:
        bench = TestBench()
        bench.simulate()


#####
# Main portion
#####

if __name__ == "__main__":
    main()