from ReBba.Components.ExiClock import ClockState, ExiClock
from ReBba.TestBenches.SimHelpers.ExiSimHelper import exiClockCycle

from amaranth.sim  import Simulator

import os

class TestBench:
    def __init__(self):
        pass

    def FlipExiClock(self, dut):
        yield dut.exiClk.eq(~dut.exiClk)

    def clockTest(self):
        dut = self.dut

        yield dut.exiClk.eq(0)
        yield
        yield from self.FlipExiClock(dut)
        yield
        assert (yield dut.exiClkState) == ClockState.RISING.value
        yield
        assert (yield dut.exiClkState) == ClockState.HIGH.value
        yield
        yield from self.FlipExiClock(dut)
        yield
        assert (yield dut.exiClkState) == ClockState.FALLING.value
        yield
        assert (yield dut.exiClkState) == ClockState.LOW.value
        yield

    def simulate(self):
        self.dut = ExiClock()

        sim = Simulator(self.dut)
        sim.add_clock(1e-6) # 1 MHz
        sim.add_sync_process(self.clockTest)

        with sim.write_vcd(os.path.dirname(os.path.abspath(__file__)) + "/ExiClock.vcd"):
            sim.run()

def main():
        bench = TestBench()
        bench.simulate()

if __name__ == "__main__":
    main()