from ReBba.Components.ExiRequest import ExiRequest

from SimHelpers.ExiSimHelper import exiClockCycle, resetDut

from amaranth import Const
from amaranth.sim import Simulator

import os

class TestBench:
    def __init__(self):
        pass

    def requestTest(self):
        dut = self.dut

        yield dut.nen.eq(Const(0))

        def afterLow0():
            assert((yield dut.requestComplete) == 0)

        def afterLow1():
            assert((yield dut.requestComplete) == 1)


        for i in range(15):
            yield dut.exiIn.eq(~dut.exiIn)
            yield from exiClockCycle(dut.exiClkState, AfterLow=afterLow0)

        yield dut.exiIn.eq(~dut.exiIn)
        yield from exiClockCycle(dut.exiClkState, AfterLow=afterLow1)

        assert((yield dut.requestComplete) == 1)
        yield from exiClockCycle(dut.exiClkState)
        assert((yield dut.requestComplete) == 1)

        yield from resetDut(dut.rst)

        for i in range(15):
            yield dut.exiIn.eq(~dut.exiIn)
            yield from exiClockCycle(dut.exiClkState, AfterLow=afterLow0)

        yield dut.exiIn.eq(~dut.exiIn)
        yield from exiClockCycle(dut.exiClkState, AfterLow=afterLow1)

    def simulate(self):
        self.dut = ExiRequest()

        sim = Simulator(self.dut)
        sim.add_clock(1e-6) # 1 MHz
        sim.add_sync_process(self.requestTest)

        with sim.write_vcd(os.path.dirname(os.path.abspath(__file__)) + "/ExiRequest.vcd"):
            sim.run()

#####
# Main portion
#####

def main():
    bench = TestBench()
    bench.simulate()

if __name__ == "__main__":
    main()