from amaranth import Elaboratable
from ReBba.Components.ShiftRegister import ShiftRegister

from ReBba.TestBenches.SimHelpers.ExiSimHelper import exiClockCycle

from amaranth.sim import Simulator

import os

class TestBench:
    def __init__(self):
        pass

    def enabled_test(self):
        dut = self.dut

        def afterAny():
            assert not (yield dut.data)

        # Disabled ShiftRegister should not Change.
        yield dut.nen.eq(1)
        for _ in range(10):
            yield dut.inb.eq(~dut.inb)
            yield from exiClockCycle(dut.exiClkState, AfterHigh=afterAny, AfterFalling=afterAny, AfterLow=afterAny, AfterRising=afterAny)

    def normal_operation(self):
        dut = self.dut

        def oracle(i):
            if i == 0: return 0x01
            if i == 1: return 0x02
            if i == 2: return 0x05
            if i == 3: return 0x0A
            if i == 4: return 0x15
            if i == 5: return 0x2A
            if i == 6: return 0x55
            if i == 7: return 0xAA
            if i == 8: return 0x55
            if i == 9: return 0xAA

        expectedOutput = 0

        def afterLow():
            assert (yield dut.data) == expectedOutput

        yield dut.nen.eq(0)
        for i in range(10):
            expectedOutput = oracle(i)
            yield dut.inb.eq(~dut.inb)
            yield from exiClockCycle(dut.exiClkState, AfterLow=afterLow)

    def simulate(self):
        self.dut = ShiftRegister(8)

        sim = Simulator(self.dut)
        sim.add_clock(1e-6) # 1 MHz
        sim.add_sync_process(self.enabled_test)

        with sim.write_vcd(os.path.dirname(os.path.abspath(__file__)) + "/ShiftRegister_enable.vcd"):
            sim.run()

        self.dut = ShiftRegister(8)

        sim = Simulator(self.dut)
        sim.add_clock(1e-6) # 1 MHz
        sim.add_sync_process(self.normal_operation)

        with sim.write_vcd(os.path.dirname(os.path.abspath(__file__)) + "/ShiftRegister_shift.vcd"):
            sim.run()

def main():
    bench = TestBench()
    bench.simulate()

if __name__ == "__main__":
    main()