from typing import Callable
from ReBba.Components.ExiClock import ClockState
from amaranth import Const, Elaboratable, Signal

def empty():
    yield None

def exiClockCycle(exiClock: Signal, AfterHigh: Callable = empty, AfterFalling: Callable = empty, AfterLow: Callable = empty, AfterRising: Callable = empty):
    yield exiClock.eq(ClockState.HIGH)
    yield
    yield from AfterHigh()
    yield

    yield exiClock.eq(ClockState.FALLING)
    yield from AfterFalling()

    yield exiClock.eq(ClockState.LOW)
    yield
    yield from AfterLow()
    yield

    yield exiClock.eq(ClockState.RISING)
    yield from AfterRising()

def resetDut(rst: Signal):
    yield
    yield rst.eq(Const(1))
    yield
    yield rst.eq(Const(0))
    yield