# re-bba-rb board — open items from hardware review (2026-07-17)

Full review of schematics + PCB against component datasheets (in
`datasheets/`), the WIZnet W5100S reference schematic, and JLCPCB
manufacturing limits. Status 2026-07-18: **all three critical findings fixed
in schematic AND PCB** (ERC 0, DRC 0 errors / 0 unconnected / 0 parity);
remaining work is the Functional/Broader/ordering lists below.

## Critical — ALL RESOLVED (schematic + PCB, verified 2026-07-18)

- [x] **EXI DO/DI swapped at J3 — FIXED 2026-07-17** (all copper unchanged).
      YAGCD SP1 naming is console-perspective: pin 6 `DO` = GC data **out** →
      adapter's MOSI *input*; pin 9 `DI` = GC data **in** ← adapter's MISO
      *output* (verified via SD Gecko: MC pin 5 DO → SD CMD input; SD2SP2:
      DO → OR gate → SD CMD). Fix applied as a pure rename/identity swap:
      - [x] SP1 pin table in `docs/gc_bba_fpga_design.md` corrected (was the
            root cause) + MISO-tristate note updated.
      - [x] Net names EXI_MOSI(_RAW) ↔ EXI_MISO(_RAW) swapped across
            `exi.kicad_sch`, `Fpga.kicad_sch`, root sheet, and the PCB — this
            also swaps the D2 (PUSB3AB6) channel assignments by name.
      - [x] R21 (22 Ω) ↔ R25 (33 Ω) identities swapped between the two
            positions so 33 Ω stays on the FPGA-driven MISO line and 22 Ω on
            the MOSI input.
      - [x] Verified: ERC 0, DRC 0 (incl. schematic parity 0), netlist:
            J3.6(DO)→R21(22Ω)→**FPGA pin 4 (IOB_8a) = EXI_MOSI in**;
            J3.9(DI)→R25(33Ω)→**FPGA pin 3 (IOB_9b) = EXI_MISO out**.
      - [ ] Use this final pin map when writing the board PCF (see Broader
            items): MOSI = pin 4, MISO = pin 3, CLK = 44 (G6), CS = 45,
            INT = 46.
- [x] **W5100S MDI termination network — DONE (schematic + PCB)**: added
      R26/R27 (49.9 Ω 1%, LCSC C25120) from
      TXOP/TXON to a common node + C18 (100 nF) to GND, and R28/R29 + C19 for
      RXIP/RXIN, on the PHY-side nets per the WIZnet reference schematic.
      ERC 0; netlist verified. PCB rework REVIEWED 2026-07-18 — PASS:
      - [x] Termination placed at U11's MDI edge (R26–R29 ~1–3 mm from pins,
            C18/C19 2.8 mm from their resistor pairs); stubs short; DRC 0
            errors incl. ETH_DP impedance rules; pair skew TX 0.30 mm /
            RX 0.72 mm; pairs on F.Cu over solid In1 GND (one short B.Cu
            crossover via per N line at the jack — fine).
      - [x] D4/D5 flow-through verified pad-by-pad (PHY side faces U11,
            cable side faces J2); In1 plane correctly voided under the
            magjack's cable/isolation side, all layers clear there.
      - [x] 3.3 Ω series dampers (WIZnet note 6) — DONE 2026-07-18: R32–R35
            (YAGEO RC0402FR-073R3L, LCSC C137986) in line U11→transformer;
            chip-side nets stay PHY_*, D4/D5-side renamed MDI_* (patterns
            added to ETH_DP netclass in .kicad_pro). Inserted in-line on the
            PCB, each in its own line row; MDI_* stubs 1.45–1.48 mm, no new
            vias; pair skew after insertion TX 0.66 mm / RX 1.81 mm (fine).
      - [x] Center-tap bypass (WIZnet note 7) — DONE 2026-07-18: C20 100 nF
            (C1525) + C21 1 µF 0603 (C15849) on ETH_3V3, placed against
            J2's pin column — as close to pins 4/5 as the In1 plane void
            allows while keeping short GND vias.
      - [x] D4/D5 (USBLC6 on the PHY pairs) — RESOLVED 2026-07-17: **keep,
            exactly as drawn.** ST explicitly rates USBLC6 for Ethernet;
            PHY-side placement guards residual coupling through the
            transformer; 2.5–3.5 pF/line is fine at 100BASE-TX. Two
            deliberate details, do not "fix": (1) pin 5 (VBUS) floats ON
            PURPOSE — the lines carry ~3.3 V DC bias (center taps) and swing
            above it; a 3.3 V-tied rail would clip signal peaks. Floating,
            the rail self-biases to the line peak and the internal 6 V zener
            still clamps strikes. (2) The split nets (PHY_* vs ETH_*) force
            FLOW-THROUGH routing (pins 1→6, 3→4 are one internal node) —
            zero-stub clamping; do NOT merge the nets or tap the diode as a
            stub (stub inductance adds L·di/dt let-through). Layout: route
            the pair in-line through the package, near J2, short GND via on
            pin 2. If ever bypassing at bring-up: desolder + jumper 1–6/3–4.
- [x] **FT2232H EEPROM interface — DONE (schematic + PCB)** per datasheet
      Table 3.4: U7.4 (DO) moved to new net EE_DO; R30 (2.2 kΩ, C25879)
      inserted EE_DO→EE_DATA; R31 (10 kΩ, C25744) pull-up EE_DO→3V3.
      EEDATA→DI stays direct. R30/R31 placed 4–5 mm from U7, routed, DRC
      parity 0. ERC 0, netlist verified, BOM fields populated.

## Functional / robustness

- [ ] **iceprog pin mismatch — schematic FIXED 2026-07-18**: FLASH_CS moved
      ADBUS3→ADBUS4 (U8 pin 21), CDONE ACBUS1→ADBUS6 (pin 23), CRESET
      ACBUS0→ADBUS7 (pin 24) — now exactly stock iceprog / iCEbreaker
      channel-A convention; old pins are NC. Pull-ups R11/R12 unchanged.
      - [ ] PCB: reroute the three lines to the new U8 pins (F8 shows the
            pad-net changes).
- [x] **TPS2116 PR1 divider margin — FIXED 2026-07-18**: R3 200k→150k
      (0402WGF1503TCE, LCSC C25755). PR1 = 1.32 V nominal; switchover at
      GC_3V3 = 2.30–2.70 V worst-case — safely below the 3.3 V rail. (Value
      change only, same footprint — no PCB work.)
- [ ] **ETH_RST pull-up — schematic FIXED 2026-07-18**: R36 10 k (C25744)
      from ETH_RST to **ETH_3V3** (low when ETH rail off).
      - [ ] PCB: place/route R36 near U11 pin 48.
- [ ] **Gateware: gate all outputs on GC_ON** — when GC_ON=0 the W5100S is
      unpowered (U12) and the GC is off, but FPGA banks stay at 3.3 V. Hold
      the W5100S bus and EXI outputs Hi-Z/low to avoid back-powering.
- [ ] **Gateware: UART crossover** — net names are FT-perspective
      (UART_TXD = FTDI output = FPGA **RX** on pin 18). Get this right in the
      board PCF.
- [ ] **Gateware: EXI INT drive style** — prefer open-drain emulation (drive
      low / release) on J3.3 rather than push-pull high.

## Broader items (beyond the wiring review — block fab on the first two)

- [ ] **Write the re-bba-rb pin constraints** — `exi_bba/synth.py` still targets
      the iCEbreaker. Full board pin map: EXI_MOSI = 4 (IOB_8a, in),
      EXI_MISO = 3 (IOB_9b, out), EXI_CLK = 44 (G6), EXI_CS = 45,
      EXI_INT = 46; W5100S bus on the IOT bank (23–43); CLK12 = 20 (G3);
      GC_ON = 21; ETH_RST = 2; UART: FPGA RX = 18 (net UART_TXD!, FTDI
      output), FPGA TX = 19; **debug: LED_G = 47 (heartbeat), LED_R = 48
      (EXI activity), DBG0–4 = 9/10/11/12/6 (J4 header)**. Pure software;
      do before ordering to prove the pinout.
- [ ] **Debug provisions — schematic DONE 2026-07-18** (was: board had none):
      - D6 green heartbeat LED (Everlight 19-217/GHC-YR1S2/3T, C72043,
        Basic) on FPGA pin 47 (LED_G) via R37 330 Ω (C25104);
      - D7 red EXI-activity LED (KENTO KT-0603R, C2286, Basic) on pin 48
        (LED_R) via R38;
      - J4 6-pin debug header (unpopulated, in_bom no): GND + DBG0–4 =
        FPGA pins 9/10/11/12/6 — route EXI CLK/CS/MOSI/MISO copies here in
        gateware for logic-analyzer bring-up;
      - TP1 3V3, TP2 1V2, TP3 ETH_3V3 (ethernet sheet), TP4 GC_ON, TP5 GND
        (1.5 mm pads, in_bom no);
      - FID1–3 fiducials placed directly on the PCB (board-only) at
        (195, 68.5)/(131, 48)/(163, 44.5) — copper-clear, DRC 0.
      - [ ] PCB: place/route the 11 schematic footprints (D6/D7, R36/R37/
            R38, TP1–5, J4) — F8 pulls them in. LEDs need visibility with
            the GC shell on: place near the RJ45/USB edge if possible.
- [ ] **Verify mechanical fit** (bench item — cannot be verified in repo):
      outline vs the SP1 slot, RJ45/USB-C protrusion vs the GC serial port
      bay opening. An earlier commit says "need to remeasure PCB outline".
      Note 2026-07-18: the J3 footprint (12 contacts, 1 mm effective pitch,
      two staggered depth rows, front-side only, fingers to the board edge
      per the .kicad_dru exception) is the geometry derived from the
      physical sp1_test_plug iterations — the test-plug project itself
      contains no reusable finger footprint to diff against, so the
      provenance is the physical test, not a file comparison.
- [x] **SP1 12 V rail viability — VERIFIED against existing projects
      (2026-07-17).** webhdx's IDE-EXI v2 for Serial Port 1 (which became the
      commercial M.2 Loader): "New switching power regulator supplies 3.3V@2A
      from 12V rail" (webhdx, gc-forever thread t=4843, 2021-08-28) — a
      shipping SP1 product powers an M.2 SATA SSD + RP2040 entirely from
      pin 5's 12 V through a buck, no external supply. That's the same
      architecture as this board at several times our load (~130 mA @ 12 V).
      webhdx moved from a linear regulator to a buck because the linear "was
      generating a lot of heat" — validating the TPS562201 choice. The
      official modem (DOL-014) was the original 12 V consumer; SP1ETH leaves
      12 V unused (runs from the 3.3 V pins). Remaining bench check only:
      - [ ] inrush into C65 (100 µF) + 2×10 µF buck input caps at GC power-on
            (the M.2 Loader precedent suggests this is a non-issue).
- [x] **FT2232H EEPROM contents + flashing workflow — DECIDED 2026-07-18**:
      ship with a **blank** 93LC46B. FT2232H falls back to its default
      config (VID 0403 / PID 6010, dual channel, MPSSE on channel A) —
      exactly what stock iceprog opens by default, which now matches the
      rewired pins. Optionally program serial/product string later with
      FT_PROG (do NOT change VID/PID, or iceprog needs -d vid:pid).
- [ ] CC1/CC2 have no ESD protection (USBLC6 covers D+/D− only) — optional,
      most hobby designs skip; note spare-channel budget if respinning D2 area.
- [x] `.history/` (embedded `.git`) — VERIFIED ignored via root
      `.gitignore:28`, nothing tracked.

## Minor / BOM

- [x] RSET_BG 12.4 k — ACCEPTED 2026-07-18 (closed, no change): datasheet
      says 12.3 kΩ, but that is an E192 value with no JLC Basic part —
      WIZnet's own reference synthesizes it as 12 k + 300 Ω. The 0.8 %
      deviation on a bandgap bias resistor is immaterial (well under the
      combined tolerance of the ref design's two 1 % parts).
- [x] Crystals Y1/Y2 — VERIFIED 2026-07-17: the BOM parts are both CL = 12 pF
      (Y1 YXC X322512MOB4SI / C70565, Y2 X322525MOB4SI / C9006, both JLC
      Basic, ±10 ppm) — correct for the 18 pF load caps and the W5100S
      Table 9 recommendation. No change needed.
- [x] 12 V-rail parts ≥ 25 V — VERIFIED in BOM audit 2026-07-17: C3/C4 25 V,
      C6 50 V, C65 25 V (Lelon SMD electrolytic); D3 SMAJ12A correct.
- [x] 1 % tolerance — VERIFIED in BOM audit 2026-07-17: R1/R2, R3/R4, R10,
      R16 are all 1 % UNI-ROYAL parts (and new R26–R35 are 1 %).
- [x] TPS22810 CT — NOT NEEDED 2026-07-18 (closed, no change): datasheet
      Table 2 shows the internal ramp dominates at low VIN — rise time at
      VIN = 3.3 V is ~98 µs even with CT = 0 (vs 102 µs at CT = 1 nF).
      Inrush ≈ 15 µF × 3.3 V / 98 µs ≈ 0.5 A for <100 µs — trivial for the
      2 A buck. A CT cap would buy nothing measurable.
- [ ] Verify HR911105A internal LED pinout (assumed: 9/12 anodes via
      R14/R15 330 Ω to ETH_3V3, 10/11 cathodes to LNKn/ACTn) and the
      Bob-Smith common on pin 8 (tied straight to GND here; WIZnet ref
      separates chassis via 1 nF/2 kV — acceptable choice, confirm intent).
- [ ] Confirm at bring-up (from CLAUDE.md): W5100S register addresses / MR
      bits were written from memory.

## JLCPCB ordering notes (DRC clean — these are order-form options)

- [ ] Stackup = JLC04121H-7628 (matches the 0.2104 mm prepreg / 0.6 mm core,
      ~1.14 mm ≙ JLC nominal 1.2 mm — satisfies the SP1 slot's 1.2 mm spec).
- [ ] Select **ENIG** (file has copper_finish "None") and **gold fingers +
      45° bevel** for the SP1 edge connector.
- [ ] Hand-solder / non-economic-assembly parts: C65 (THT electrolytic),
      J2 magjack (THT), J1 USB-C, D2 (DFN2111-7, tiny). Plan assembly split.
- [x] LCSC part numbers — COMPLETE 2026-07-17: all 112 orderable components
      have Footprint + Value + MPN + LCSC + Manufacturer (netlist-vs-BOM
      count check passes; the only netlist/BOM delta is J3, deliberately
      excluded from BOM since the SP1 edge connector is PCB gold fingers,
      not a part). 12 V-rail caps verified ≥25 V, divider/REF/RSET resistors
      verified 1 %. Note: D2 is the **ElecSuper** PUSB3AB6Z(ES) clone
      (C49383400, Extended), not Nexperia — same DFN-7 1.1×2.1 / 0.15 pF;
      pin-compatible, but treat as a bring-up suspect if EXI ESD behaviour
      looks odd. C65 is an SMD electrolytic (Lelon VZH101M1ETR-0607, 25 V) —
      assembly-friendly, not THT as first assumed.
- [ ] Fiducials: VERIFIED ABSENT (0 on the board, 2026-07-18). JLCPCB can
      panel-add their own, but 3 board fiducials (1 mm copper dot, 2 mm mask
      opening, asymmetric corners) is the robust choice — add with the debug
      LEDs/test points pass.

## Housekeeping (repo) — done 2026-07-17

- [x] Restored `hardware/re-bba-rb/datasheets/` (deleted by `3547302`) from
      the LFS store; added TPS22810 (power/) and PUSB3AB6 (exi/) datasheets
      that were missing from the original set.
- [x] Deleted stale lowercase `power.kicad_sch` (the pre-rework draft from the
      first power-sheet commit; live sheet is `Power.kicad_sch`). It "kept
      coming back" because both paths were git-tracked: on a case-insensitive
      (Windows) checkout they are one file on disk, so deleting one path also
      deletes the other, and restoring the live sheet re-materialises both —
      the next commit resurrects the stale path. Removing the lowercase path
      from the git index (done from the case-sensitive devcontainer) is the
      permanent fix. **Never add two files differing only in case.**
- [x] Deleted `re-bba-rb.kicad_pcb.old.kicad_pcb` / `.old.kicad_pro` leftovers
      (recoverable from git history if ever needed).

## Verified correct — do not re-flag

TPS562201 (EN at 12 V legal, abs max 19 V; 0.768 V ref × 33k/10k = 3.30 V;
L/C per Table 7-2) · TPS2116 mode/ST logic (GC priority, USB fallback,
GC_ON polarity) · AP2112K ×2 · TPS22810 EN (never floats, R5 pull-up) ·
**FT2232H VPHY/VPLL on 3.3 V is correct per datasheet** (the VCORE→3V3
relabel at HEAD was a fix) · W5100S parallel-mode straps (MOD=0100, SCLK→GND,
pin32=A0/pin33=A1, INTn push-pull, internal pull-ups on CSn/RDn/WRn/DAT) ·
W5100S 1V2 loop + mandatory 1 MΩ crystal feedback · PUSB3AB6 pinout/footprint ·
USB-C CC/ESD wiring · iCE40 power/config/flash, CLK12 on G3, EXI_CLK on G6 ·
magjack transformer spec (1:1, 350 µH) · PCB vs JLCPCB capability floor
(rules in `re-bba-rb.kicad_dru`, 0 DRC errors).
