# re-bba-rb board — open items from hardware review (2026-07-17)

> **Status 2026-08-02:** board is **DRC-clean in the KiCad GUI and all BOM
> parts are picked** (eFuse U13 + R43–R47/C66, RExt R44, EE_CS R43, D13, all
> verified present with MPN+LCSC in the live schematic/PCB). ⚠️ **Do not trust
> `kicad-cli pcb drc` blindly** — it does not refill zones and will report
> phantom GND-via-in-3V3-pour / thermal-pad clearance "errors" (actual 0.000 mm)
> that the GUI resolves on refill. See REVIEW.md §7. The per-session DRC counts
> quoted lower in this file predate the 2026-07-31 eFuse work; the GUI is the
> authority and it is clean. Remaining work is bench/verification + JLC
> order-form options, not schematic/PCB defects.


Full review of schematics + PCB against component datasheets (in
`datasheets/`), the WIZnet W5100S reference schematic, and JLCPCB
manufacturing limits. Status 2026-07-18: **all three critical findings fixed
in schematic AND PCB** (ERC 0, DRC 0 errors / 0 unconnected / 0 parity);
remaining work is the Functional/Broader/ordering lists below.

**Status 2026-07-22 (last-check pass):** ERC still clean (2 known-benign
`lib_symbol_issues` on the generic Q_NPN_BEC/Q_PNP_BEC library symbols, not
real problems). DRC: 0 unconnected items board-wide (incl. J3 — all 24 pads
now carry real net copper, confirmed by direct pad/net inspection, not just
the ratsnest count); 242 total violations, of which only **4 are errors**
(2× `clearance` + 2× `hole_clearance`, two GND vias at (190.78/190.34, 58.58)
0 mm from the `/Power/3V3` zone on In2.Cu — see Functional/robustness below),
1 `track_dangling` (a 0.06 mm stub on `/exi/EXI_MOSI_RAW` near (188.39,
57.52), likely harmless routing debris), and the rest are silkscreen
warnings (171 overlap, 60 over-copper, 6 edge-clearance). This session also
did extensive photo-based mechanical verification and a real J3 Y-position
correction — see "Verify mechanical fit" below — and re-added fiducials with
a different footprint/position than this file previously documented.

**Status 2026-07-24 (major session):** ERC 0 (same 2 known-benign warnings +
1 expected `power_pin_not_driven` on J5's `EXI_GND`, see below — not a real
problem, that net has no power-symbol driver by design). DRC: 0 unconnected
items, 280 total violations — same silkscreen-warning baseline as before
plus `npth_inside_courtyard` (27, J5's mouse-bite holes sit close to J2's
courtyard, judged benign — holes, not a component body) and 1 harmless
`track_dangling`. The 2 GND-vias-vs-3V3-zone short from 2026-07-22 is
**gone** (resolved somewhere in this session's PCB work, confirmed via fresh
DRC). Gerbers/BOM/CPL all regenerated and verified current as of this pass.
Major work this session:
- **D6/D8/D9/D12 green LEDs swapped** Everlight 19-217/GHC-YR1S2/3T (C72043,
  out of stock) → Hubei KENTO KT-0603G (C12624) — same 0603 footprint, same
  manufacturer family as the already-used red KT-0603R (D7/D11). Series
  resistors R37/R41/R42 changed 330 Ω → **49.9 Ω** (reused C25120, the same
  part already on R26–R29 — no new BOM line) to compensate for KT-0603G's
  higher Vf (3.1 V typ.) and restore comparable brightness (~4 mA vs the
  ~0.6 mA the old resistor value would have given it). D12/D13 (RGB channels,
  driven directly by the FPGA's `SB_RGBA_DRV` hard macro, no series resistor)
  need no resistor change — flagged as slightly reduced current-source
  headroom at the higher Vf, not fixed (nothing to fix, no resistor exists).
  - [x] **D13 and the 10 kΩ resistor — COMMITTED in the live BOM**
        (verified 2026-08-02): D13 = Hubei KENTO **KT-0603Y (C2287)**; the
        10 kΩ 0402 = UNI-ROYAL 0402WGF1002TCE **C25744** (R43 and others).
        These are the chosen parts, no longer unresolved.
        - [ ] Standard order-time step (not a blocker, applies to the whole
              BOM): do a **live JLCPCB stock check** just before ordering —
              earlier web-search stock claims proved unreliable, so trust
              only the JLCPCB part page at order time. C2287 and C25744 were
              the out-of-stock scares that prompted this note; re-confirm them
              specifically.
- **J5 added**: a second SP1 gold-finger connector, footprint copied from
  the eth2sp1 open-source project (github.com/jochemvdmeulen/eth2sp1),
  library file `hardware/SP1_eth2sp1_reference.kicad_mod`. Real purpose:
  hand-solder insert for J3 — J5 is fabricated on this same board/panel via
  a mouse-bite tab, snapped off after production, and soldered onto J3 so
  its gold fingers protrude past the board edge into the GC slot (J3 itself
  uses thru-hole insert pads, not bare gold fingers). Pad length tuned to
  13.5 mm + board thickness (1.1412 mm) = 14.6412 mm, then trimmed −1.0 mm to
  **13.6412 mm** (near/board-edge-side pad edge held fixed 0.6 mm off the
  nose throughout, matching eth2sp1's original tip clearance). J5 pins
  1,3–10 stay no-connect (DNP, no live signals); pins 2/11/12 (shield/ground)
  tie to a new **`EXI_GND`** net — a dedicated reference-plane net for the
  fingers, deliberately kept separate from board `GND` until physically
  joined to J3 by solder (J5 is a separate PCB fragment until then).
  - [x] Mouse-bite tab: 27× 0.4 mm NPTH holes at X=106.8900, spanning the
        full Y=48.1–66.6 tongue height (both endpoints landing on the
        original tongue corners as half-moon scallops) — footprint
        `MouseBites_J5`. **Has disappeared from the PCB and needed
        re-adding twice this session** (cause unknown — likely an
        accidental GUI selection/delete, watch for a third time).
  - [ ] **User is routing the `EXI_GND` reference plane + stitching vias
        under J5's fingers** — in progress, not finished. Guidance given:
        multiple vias per ground pad (not just one via per pin), plus
        stitching vias flanking the *signal* fingers (CLK/MOSI/MISO/CS)
        too, not just the 3 named ground pins — that's what actually
        controls impedance at the trace-to-finger transition.
  - [ ] J2's `HANRUN_HR911105A.kicad_mod` footprint has a cosmetic-only
        defect: pads 15/16 (2.445 mm ground/shield tabs) stick out ~0.97 mm
        past the F.Fab body-outline rectangle (top and bottom, symmetric).
        **Confirmed NOT a DRC/manufacturability issue** — the real courtyard
        (F.CrtYd) properly encloses both pads with ~0.28 mm margin; this is
        why JLCPCB's placement-preview render looked alarming (it draws the
        undersized F.Fab rectangle as the "body"). Offered to fix the F.Fab
        rectangle for cosmetic accuracy; not done.
- **Gateware pin constraints — DONE** (was the "Write the re-bba-rb pin
  constraints" item below, now resolved): `exi_bba/synth.py`'s
  `IceBreakerPlatform` no longer targets the iCEbreaker — every pin pulled
  directly from the schematic netlist and verified placed by nextpnr.
  Also fixed two real bugs found in the process: **LED polarity was
  backwards** (D6/D7 are active-high on this board, opposite the
  iCEbreaker's onboard active-low LEDs the old code assumed) and **removed
  a reference to a physical button that doesn't exist on this board** (the
  iCEbreaker's `BTN_N` was dev-board-only; `panel_btn` now ties idle).
  - [x] **Real hardware conflict found and fixed**: the schematic originally
        put `ETH_INT` on U9 pin 35, which **physically conflicts with the
        iCE40UP5K's PLL hard macro** — pin 35 cannot be used as an *input*
        while the PLL is instantiated (confirmed both by nextpnr's own chip
        database and by direct testing: an unrelated input signal swapped
        onto pin 35 reproduces the identical conflict; an *output* signal
        on pin 35 works fine — the restriction is input-direction-specific,
        not a blanket "pin 35 is unusable"). Board was still in design, so
        fixed at the source: **`ETH_INT` moved from U9 pin 35 to pin 13**
        (schematic + PCB both reworked and verified — pin 13 was confirmed
        via icestorm's own pin database to be the *only* spare GPIO on this
        exact SG48 package/board combo; all other 38 usable pins were
        already assigned). PCB reroute done and DRC-clean (0 unconnected,
        0 shorts). An alternative (wr_n 36→35, rd_n 37→36, int_n→37, keeping
        ETH_INT physically clustered with the rest of the ethernet bus) was
        evaluated and rejected — it works but only found 1 passing seed out
        of 5 tried, with much thinner timing margin (0.4% vs 3%) than the
        pin-13 arrangement.
  - [x] **Timing verified — closes, seed-sensitive**: seed 1 narrowly missed
        (`capture_clk` 53.08 MHz vs 54.02 MHz target), seed 3 passes both
        domains cleanly (`clk` 37.82 MHz vs 24 MHz, `capture_clk` 55.69 MHz
        vs 54.02 MHz) — consistent with this design's known seed-sensitivity
        (routing-dominated at ~22% LC utilization). `build/top.bin` on disk
        is the seed-3 result. Re-verified after the PCB reroute — identical
        numbers, as expected (PCB copper doesn't affect FPGA-internal
        timing).
  - [ ] **Known bug, not fixed**: `synth.py`'s built-in `--seeds N` sweep
        loop throws silent exceptions on seeds after the first when run in
        one process (pre-existing, unrelated to this session's pin changes)
        — worked around by invoking each seed as a separate process. The
        convenience one-command multi-seed workflow needs debugging if
        wanted again.

## Critical — ALL RESOLVED (schematic + PCB, verified 2026-07-18)

- [x] **EXI DO/DI swapped at J3 — FIXED 2026-07-17** (all copper unchanged).
      YAGCD SP1 naming is console-perspective: pin 6 `DO` = GC data **out** →
      adapter's MOSI *input*; pin 9 `DI` = GC data **in** ← adapter's MISO
      *output* (verified via SD Gecko: MC pin 5 DO → SD CMD input; SD2SP2:
      DO → OR gate → SD CMD). Fix applied as a pure rename/identity swap:
      - [x] SP1 pin table in `docs/gc_bba_fpga_design.md` corrected (was the
            root cause) + MISO-tristate note updated.
      - [x] Net names EXI_MOSI(_RAW) ↔ EXI_MISO(_RAW) swapped across
            `exi.kicad_sch`, `Fpga.kicad_sch`, root sheet, and the PCB — this
            also swaps the D2 (PUSB3AB6) channel assignments by name.
      - [x] R21 (22 Ω) ↔ R25 (33 Ω) identities swapped between the two
            positions so 33 Ω stays on the FPGA-driven MISO line and 22 Ω on
            the MOSI input.
      - [x] Verified: ERC 0, DRC 0 (incl. schematic parity 0), netlist:
            J3.6(DO)→R21(22Ω)→**FPGA pin 4 (IOB_8a) = EXI_MOSI in**;
            J3.9(DI)→R25(33Ω)→**FPGA pin 3 (IOB_9b) = EXI_MISO out**.
      - [ ] Use this final pin map when writing the board PCF (see Broader
            items): MOSI = pin 4, MISO = pin 3, CLK = 44 (G6), CS = 45,
            INT = 46.
- [x] **W5100S MDI termination network — DONE (schematic + PCB)**: added
      R26/R27 (49.9 Ω 1%, LCSC C25120) from
      TXOP/TXON to a common node + C18 (100 nF) to GND, and R28/R29 + C19 for
      RXIP/RXIN, on the PHY-side nets per the WIZnet reference schematic.
      ERC 0; netlist verified. PCB rework REVIEWED 2026-07-18 — PASS:
      - [x] Termination placed at U11's MDI edge (R26–R29 ~1–3 mm from pins,
            C18/C19 2.8 mm from their resistor pairs); stubs short; DRC 0
            errors incl. ETH_DP impedance rules; pair skew TX 0.30 mm /
            RX 0.72 mm; pairs on F.Cu over solid In1 GND (one short B.Cu
            crossover via per N line at the jack — fine).
      - [x] D4/D5 flow-through verified pad-by-pad (PHY side faces U11,
            cable side faces J2); In1 plane correctly voided under the
            magjack's cable/isolation side, all layers clear there.
      - [x] 3.3 Ω series dampers (WIZnet note 6) — DONE 2026-07-18: R32–R35
            (YAGEO RC0402FR-073R3L, LCSC C137986) in line U11→transformer;
            chip-side nets stay PHY_*, D4/D5-side renamed MDI_* (patterns
            added to ETH_DP netclass in .kicad_pro). Inserted in-line on the
            PCB, each in its own line row; MDI_* stubs 1.45–1.48 mm, no new
            vias; pair skew after insertion TX 0.66 mm / RX 1.81 mm (fine).
      - [x] Center-tap bypass (WIZnet note 7) — DONE 2026-07-18: C20 100 nF
            (C1525) + C21 1 µF 0603 (C15849) on ETH_3V3, placed against
            J2's pin column — as close to pins 4/5 as the In1 plane void
            allows while keeping short GND vias.
      - [x] D4/D5 (USBLC6 on the PHY pairs) — RESOLVED 2026-07-17: **keep,
            exactly as drawn.** ST explicitly rates USBLC6 for Ethernet;
            PHY-side placement guards residual coupling through the
            transformer; 2.5–3.5 pF/line is fine at 100BASE-TX. Two
            deliberate details, do not "fix": (1) pin 5 (VBUS) floats ON
            PURPOSE — the lines carry ~3.3 V DC bias (center taps) and swing
            above it; a 3.3 V-tied rail would clip signal peaks. Floating,
            the rail self-biases to the line peak and the internal 6 V zener
            still clamps strikes. (2) The split nets (PHY_* vs ETH_*) force
            FLOW-THROUGH routing (pins 1→6, 3→4 are one internal node) —
            zero-stub clamping; do NOT merge the nets or tap the diode as a
            stub (stub inductance adds L·di/dt let-through). Layout: route
            the pair in-line through the package, near J2, short GND via on
            pin 2. If ever bypassing at bring-up: desolder + jumper 1–6/3–4.
- [x] **FT2232H EEPROM interface — DONE (schematic + PCB)** per datasheet
      Table 3.4: U7.4 (DO) moved to new net EE_DO; R30 (2.2 kΩ, C25879)
      inserted EE_DO→EE_DATA; R31 (10 kΩ, C25744) pull-up EE_DO→3V3.
      EEDATA→DI stays direct. R30/R31 placed 4–5 mm from U7, routed, DRC
      parity 0. ERC 0, netlist verified, BOM fields populated.

## Functional / robustness

- [x] **iceprog pin mismatch — schematic FIXED 2026-07-18, PCB rerouted**:
      FLASH_CS moved ADBUS3→ADBUS4 (U8 pin 21), CDONE ACBUS1→ADBUS6 (pin 23),
      CRESET ACBUS0→ADBUS7 (pin 24) — now exactly stock iceprog / iCEbreaker
      channel-A convention; old pins are NC. Pull-ups R11/R12 unchanged.
      Verified 2026-07-22: 0 DRC violations in the U8 pin area, 0 unconnected
      items board-wide.
- [x] **TPS2116 PR1 divider margin — FIXED 2026-07-18**: R3 200k→150k
      (0402WGF1503TCE, LCSC C25755). PR1 = 1.32 V nominal; switchover at
      GC_3V3 = 2.30–2.70 V worst-case — safely below the 3.3 V rail. (Value
      change only, same footprint — no PCB work.)
- [x] **ETH_RST pull-up — schematic FIXED 2026-07-18, PCB placed/routed**:
      R36 10 k (C25744) from ETH_RST to **ETH_3V3** (low when ETH rail off),
      at (148.49, 61.7225) near U11 pin 48. Verified 2026-07-22: nets
      `/ethernet/ETH_RST` + `/ethernet/ETH_3V3` both present on the footprint,
      0 unconnected items.
- [ ] **12 V inrush limiter (U13 TPS25961 eFuse) — SCHEMATIC DONE 2026-07-31**,
      full design rationale in REVIEW.md §6. J3.5 → 12V_RAW → U13 → 12V_EXI;
      D3 (TVS) stays upstream, C65 downstream. R45 100 k sets I_LIM ≈ 500 mA
      (caps inrush, 3.8× the ~130 mA steady-state load); R46/R47 620 k/100 k
      set UVLO ≈ 8.9 V; C66 100 nF is Cin. U13 = TPS25961DRVR, **LCSC
      C5571272**.
      - [x] **PCB: U13, R45, R46, R47, C66 placed + routed** (verified on disk
            2026-08-02: U13 at 206.99,48.47 with R45/R46/R47/C66 clustered
            around it; 0 unconnected items board-wide). Two datasheet
            requirements honoured in layout: (1) the **thermal pad connects to
            the GND plane** — footprint is the `_ThermalVias` variant; (2)
            **OVLO absolute max 6.5 V** tied to GND for the internal fixed
            threshold. Keep this arrangement.
      - [x] **Parts for R45/R46/R47/C66 — PICKED** (verified in live BOM
            2026-08-02): R45/R47 = UNI-ROYAL 100 k **C25741**, R46 = YAGEO
            620 k RC0402FR-07620KL **C137952**, C66 = 100 nF **C1525**.
            R45 = 100 k is clear of the forbidden ON-resistance bins
            (58.8–66.7 kΩ, 111–142 kΩ, 250–500 kΩ) — do not "round" it into
            them if ever re-selected.
      - [ ] **Bench: verify inrush at GC power-on** — expect ≈500 mA for
            ~2.9 ms (was ~621 mA slew-limited, unbounded before the eFuse).
            Also confirm no retry/motorboating at startup; if the rail sags
            more than expected, that points at SP1 connector/cable impedance,
            not the UVLO setting.
- [ ] **Gateware: gate all outputs on GC_ON** — when GC_ON=0 the W5100S is
      unpowered (U12) and the GC is off, but FPGA banks stay at 3.3 V. Hold
      the W5100S bus and EXI outputs Hi-Z/low to avoid back-powering.
- [ ] **Gateware: UART crossover** — net names are FT-perspective
      (UART_TXD = FTDI output = FPGA **RX** on pin 18). Get this right in the
      board PCF.
- [ ] **Gateware: EXI INT drive style** — prefer open-drain emulation (drive
      low / release) on J3.3 rather than push-pull high.
- [ ] **New 2026-07-22: 2 GND vias short the `/Power/3V3` zone on In2.Cu** —
      found during the last DRC pass, 4 error-severity violations (2×
      `clearance` + 2× `hole_clearance`, both 0 mm actual). Two GND vias at
      (190.78, 58.58) and (190.34, 58.58) — just south of J3's courtyard,
      likely stitching vias added during the J3 reroute — sit directly on
      top of the 3V3 pour on In2.Cu. This is a real short risk, not a
      manufacturability nit: move or delete these two vias (or void the 3V3
      zone locally) before ordering. Also 1 harmless `track_dangling`: a
      0.06 mm stub on `/exi/EXI_MOSI_RAW` near (188.39, 57.52) — routing
      debris, delete when convenient.

## Broader items (beyond the wiring review — block fab on the first two)

- [x] **Write the re-bba-rb pin constraints — DONE 2026-07-24**, see the
      "Status 2026-07-24" note at the top for full details. Real board pin
      map: EXI_MOSI = 4 (IOB_8a, in), EXI_MISO = 3 (IOB_9b, out),
      EXI_CLK = 44 (G6), EXI_CS = 45, EXI_INT = 46; W5100S bus A0=42 A1=38
      D0-D7=34/32/31/28/27/26/25/23 CS_N=43 RD_N=37 WR_N=36 RST_N=2;
      **ETH_INT moved from the schematic's original pin 35 to pin 13** (pin
      35 physically conflicts with the PLL for input use — hardware
      constraint, not fixable in software, resolved via schematic+PCB
      rework since the board was still in design); CLK12 = 20 (G3);
      UART: FPGA RX = 18 (net UART_TXD!, FTDI output), FPGA TX = 19;
      debug: LED_G = 47 (heartbeat, active-high), LED_R = 48 (EXI activity,
      active-high), DBG0–4 = 9/10/11/12/6 (J4 header). No physical button
      on this board — the old iCEbreaker BTN_N reference was removed.
      Placement + timing verified (nextpnr, seed 3: clk 37.82 MHz/24 target,
      capture_clk 55.69 MHz/54.02 target, both PASS).
- [ ] **Debug provisions — schematic DONE 2026-07-18** (was: board had none):
      - D6 green heartbeat LED (**Hubei KENTO KT-0603G, C12624** — swapped
        2026-07-24, Everlight original was out of stock) on FPGA pin 47
        (LED_G) via R37 **49.9 Ω** (C25120, swapped from 330 Ω same day to
        compensate for KT-0603G's higher Vf — see the 2026-07-24 status note);
      - D7 red EXI-activity LED (KENTO KT-0603R, C2286, Basic) on pin 48
        (LED_R) via R38 (unchanged, this one was never out of stock);
      - J4 6-pin debug header (unpopulated, in_bom no): GND + DBG0–4 =
        FPGA pins 9/10/11/12/6 — route EXI CLK/CS/MOSI/MISO copies here in
        gateware for logic-analyzer bring-up;
      - TP1 3V3, TP2 1V2, TP3 ETH_3V3 (ethernet sheet), TP4 GC_ON, TP5 GND
        (1.5 mm pads, in_bom no);
      - FID1–3 fiducials: **superseded 2026-07-22**, see the fiducials entry
        under "JLCPCB ordering notes" below for current footprint/positions.
      - [x] **PCB: place/route the 11 schematic footprints — DONE**, verified
            2026-07-22: D6/D7/R37/R38/TP1–5/J4 all present with correct net
            assignments (`Net-(D6-A)`/`Net-(D7-A)`/`/fpga/LED_G`/`/fpga/LED_R`
            for the LEDs, `/Power/3V3`/`/fpga/1V2`/`/ethernet/ETH_3V3`/
            `/GC_ON`/`GND` for TP1–5, `/fpga/DBG0-4`+`GND` for J4), 0
            unconnected items. LED visibility vs the GC shell not
            re-verified here (bench item).
- [x] **Verify mechanical fit — major progress 2026-07-22** (bench item,
      photo-based, this session): the user measured the real GameCube SP1
      bay using an Android reference-square app (ImageMeter) against a 2 cm
      calibration square, photographing up into the bay with J2 (Ethernet
      jack) as the fixed anchor. Cross-referencing those measurements against
      the PCB's J3/J2 courtyards (courtyard, not pad or slot, is the correct
      mechanical reference) found J3 was mispositioned in Y by ~5 mm.
      Orientation (which real-world edge maps to which PCB edge) was
      independently confirmed via a numerical fit check (original pairing:
      ~2–3 mm residual both sides; a candidate 180°-about-X-axis reflection
      was tested and rejected: 6.3 mm residual on one side) plus a rendered
      PCB PDF sanity check.
      - [x] **J3 shifted**: `(at 189.85 59.9)` → `(at 189.85 54.9)`, i.e.
            **Y −5.0 mm**, X unchanged (X was checked against both bay edges
            using the board's true front/back edges — no shift needed). J3
            was fully unrouted at shift time (0 track segments touched any
            of its 24 pads, verified beforehand) so the move was electrically
            free; the resulting 183 DRC collisions (D2 + EXI_* net clearances
            in the new J3 footprint area) have since been resolved by
            rerouting — 0 J3-area DRC errors remain as of 2026-07-22, and J3
            is now fully routed (see above).
      - [ ] X/Y still not verified against real hardware — this was a
            photo/measurement-based correction, not a fit-check against an
            actual GameCube. Confirm on the bench when a unit is available.
      - [ ] Insertion depth (Z, connector engagement into the slot) —
            explicitly deferred by the user, not addressed this pass.
      - Note 2026-07-18 (unchanged): the J3 footprint (12 contacts, 1 mm
            effective pitch, two staggered depth rows, front-side only,
            fingers to the board edge per the .kicad_dru exception) is the
            geometry derived from the physical sp1_test_plug iterations —
            the test-plug project itself contains no reusable finger
            footprint to diff against, so the provenance is the physical
            test, not a file comparison.
- [x] **SP1 12 V rail viability — VERIFIED against existing projects
      (2026-07-17).** webhdx's IDE-EXI v2 for Serial Port 1 (which became the
      commercial M.2 Loader): "New switching power regulator supplies 3.3V@2A
      from 12V rail" (webhdx, gc-forever thread t=4843, 2021-08-28) — a
      shipping SP1 product powers an M.2 SATA SSD + RP2040 entirely from
      pin 5's 12 V through a buck, no external supply. That's the same
      architecture as this board at several times our load (~130 mA @ 12 V).
      webhdx moved from a linear regulator to a buck because the linear "was
      generating a lot of heat" — validating the TPS562201 choice. The
      official modem (DOL-014) was the original 12 V consumer; SP1ETH leaves
      12 V unused (runs from the 3.3 V pins). Remaining bench check only:
      - [ ] inrush into C65 (100 µF) + 2×10 µF buck input caps at GC power-on
            (the M.2 Loader precedent suggests this is a non-issue).
- [x] **FT2232H EEPROM contents + flashing workflow — DECIDED 2026-07-18**:
      ship with a **blank** 93LC46B. FT2232H falls back to its default
      config (VID 0403 / PID 6010, dual channel, MPSSE on channel A) —
      exactly what stock iceprog opens by default, which now matches the
      rewired pins. Optionally program serial/product string later with
      FT_PROG (do NOT change VID/PID, or iceprog needs -d vid:pid).
- [ ] CC1/CC2 have no ESD protection (USBLC6 covers D+/D− only) — optional,
      most hobby designs skip; note spare-channel budget if respinning D2 area.
- [x] `.history/` (embedded `.git`) — VERIFIED ignored via root
      `.gitignore:28`, nothing tracked.

## Minor / BOM

- [x] RSET_BG 12.4 k — ACCEPTED 2026-07-18 (closed, no change): datasheet
      says 12.3 kΩ, but that is an E192 value with no JLC Basic part —
      WIZnet's own reference synthesizes it as 12 k + 300 Ω. The 0.8 %
      deviation on a bandgap bias resistor is immaterial (well under the
      combined tolerance of the ref design's two 1 % parts).
- [x] Crystals Y1/Y2 — VERIFIED 2026-07-17, **RE-CONFIRMED 2026-07-31**: the
      BOM parts are both CL = 12 pF (Y1 YXC X322512MOB4SI / C70565,
      Y2 X322525MOB4SI / C9006, both JLC Basic, ±10 ppm) — correct for the
      18 pF load caps (`CL = C/2 + Cstray` → 18/2 + 3 = 12 pF exactly).
      **This entry was right; a 2026-07-31 attempt to change the caps to
      30 pF/10 pF was a regression and has been reverted.** The cause was
      wrong `CL` metadata in the schematic symbol properties (Y1 said 18 pF,
      Y2 said 8 pF) — properties are now corrected to the real specs from
      `datasheets/Ysx321SL.pdf`. Do not change the crystal caps.
      Note: the "W5100S Table 9 recommendation" citation above is fragile —
      Table 9 says 12 pF but **Table 8 says 8 pF**, and the DS revision
      history logs "Modified Load capacitance value (12p → 8p)". The fitted
      12 pF part therefore matches the *stale* table. Accepted as a
      documented deviation (frequency accuracy unaffected; gain margin 7.75×
      with R44) — see REVIEW.md §5.
- [x] 12 V-rail parts ≥ 25 V — VERIFIED in BOM audit 2026-07-17: C3/C4 25 V,
      C6 50 V, C65 25 V (Lelon SMD electrolytic); D3 SMAJ12A correct.
- [x] 1 % tolerance — VERIFIED in BOM audit 2026-07-17: R1/R2, R3/R4, R10,
      R16 are all 1 % UNI-ROYAL parts (and new R26–R35 are 1 %).
- [x] TPS22810 CT — NOT NEEDED 2026-07-18 (closed, no change): datasheet
      Table 2 shows the internal ramp dominates at low VIN — rise time at
      VIN = 3.3 V is ~98 µs even with CT = 0 (vs 102 µs at CT = 1 nF).
      Inrush ≈ 15 µF × 3.3 V / 98 µs ≈ 0.5 A for <100 µs — trivial for the
      2 A buck. A CT cap would buy nothing measurable.
- [ ] Verify HR911105A internal LED pinout (assumed: 9/12 anodes via
      R14/R15 330 Ω to ETH_3V3, 10/11 cathodes to LNKn/ACTn) and the
      Bob-Smith common on pin 8 (tied straight to GND here; WIZnet ref
      separates chassis via 1 nF/2 kV — acceptable choice, confirm intent).
- [ ] Confirm at bring-up (from CLAUDE.md): W5100S register addresses / MR
      bits were written from memory.
- [ ] **Measure Y2 crystal drive level at bring-up and tune R44 (RExt) if
      needed.** Fitted at **49.9 Ω** (part PICKED: UNI-ROYAL 0402WGF4999TCE
      **C25120**, verified in live BOM 2026-08-02). Gain margin 7.53× (DS
      requires ≥5; **ceiling 100 Ω**, 120 Ω fails startup). Reason it exists:
      the fitted crystal is rated **DL = 200 µW max** but W5100S Table 9 says
      select a **500 µW** part, so the chip can overdrive it ~2.5×. Only a
      bench action remains: scope the crystal, compute DL; if comfortably under
      200 µW a smaller value (or 0 Ω per the WIZnet reference) is fine, if high
      go up but stay ≤100 Ω. See REVIEW.md §5.
- [x] **R43 part PICKED** (EE_CS 10 kΩ pull-down): UNI-ROYAL 0402WGF1002TCE
      **C25744** (verified in live BOM 2026-08-02). No action remains.

## JLCPCB ordering notes (DRC clean — these are order-form options)

- [ ] Stackup = JLC04121H-7628 (matches the 0.2104 mm prepreg / 0.6 mm core,
      ~1.14 mm ≙ JLC nominal 1.2 mm — satisfies the SP1 slot's 1.2 mm spec).
- [ ] Select **ENIG** (file has copper_finish "None") and **gold fingers +
      45° bevel** for the SP1 edge connector.
- [ ] Hand-solder / non-economic-assembly parts: C65 (THT electrolytic),
      J2 magjack (THT), J1 USB-C, D2 (DFN2111-7, tiny). Plan assembly split.
- [x] LCSC part numbers — COMPLETE 2026-07-17: all 112 orderable components
      have Footprint + Value + MPN + LCSC + Manufacturer (netlist-vs-BOM
      count check passes; the only netlist/BOM delta is J3, deliberately
      excluded from BOM since the SP1 edge connector is PCB gold fingers,
      not a part). 12 V-rail caps verified ≥25 V, divider/REF/RSET resistors
      verified 1 %. Note: D2 is the **ElecSuper** PUSB3AB6Z(ES) clone
      (C49383400, Extended), not Nexperia — same DFN-7 1.1×2.1 / 0.15 pF;
      pin-compatible, but treat as a bring-up suspect if EXI ESD behaviour
      looks odd. C65 is an SMD electrolytic (Lelon VZH101M1ETR-0607, 25 V) —
      assembly-friendly, not THT as first assumed.
- [x] Fiducials: **placed 2026-07-22** — `Fiducial_0.5mm_Mask1mm` (0.5 mm
      copper dot, 1 mm mask opening; downsized from the originally-planned
      1 mm/2 mm footprint because no spot on the real board had >5 mm
      clearance from other parts) at FID1 (160.0, 50.5), FID2 (184.2, 61.0),
      FID3 (187.3, 47.5) — asymmetric placement, all verified genuinely
      on-board against the true (non-bounding-box) board polygon, DRC 0.

## Housekeeping (repo) — done 2026-07-17

- [x] Restored `hardware/re-bba-rb/datasheets/` (deleted by `3547302`) from
      the LFS store; added TPS22810 (power/) and PUSB3AB6 (exi/) datasheets
      that were missing from the original set.
- [x] Deleted stale lowercase `power.kicad_sch` (the pre-rework draft from the
      first power-sheet commit; live sheet is `Power.kicad_sch`). It "kept
      coming back" because both paths were git-tracked: on a case-insensitive
      (Windows) checkout they are one file on disk, so deleting one path also
      deletes the other, and restoring the live sheet re-materialises both —
      the next commit resurrects the stale path. Removing the lowercase path
      from the git index (done from the case-sensitive devcontainer) is the
      permanent fix. **Never add two files differing only in case.**
- [x] Deleted `re-bba-rb.kicad_pcb.old.kicad_pcb` / `.old.kicad_pro` leftovers
      (recoverable from git history if ever needed).

## Verified correct — do not re-flag

TPS562201 (EN at 12 V legal, abs max 19 V; 0.768 V ref × 33k/10k = 3.30 V;
L/C per Table 7-2) · TPS2116 mode/ST logic (GC priority, USB fallback,
GC_ON polarity) · AP2112K ×2 · TPS22810 EN (never floats, R5 pull-up) ·
**FT2232H VPHY/VPLL on 3.3 V is correct per datasheet** (the VCORE→3V3
relabel at HEAD was a fix) · W5100S parallel-mode straps (MOD=0100, SCLK→GND,
pin32=A0/pin33=A1, INTn push-pull, internal pull-ups on CSn/RDn/WRn/DAT) ·
W5100S 1V2 loop + mandatory 1 MΩ crystal feedback · PUSB3AB6 pinout/footprint ·
USB-C CC/ESD wiring · iCE40 power/config/flash, CLK12 on G3, EXI_CLK on G6 ·
magjack transformer spec (1:1, 350 µH) · PCB vs JLCPCB capability floor
(rules in `re-bba-rb.kicad_dru`, 0 DRC errors).
