(version 1)

# SP1 edge-connector (J3): the gold fingers must reach the board edge to make
# contact in the GameCube slot, so copper-to-edge clearance is intentionally
# relaxed for this footprint only. This is by design, not a defect.
# Test BOTH items because the violated pair is (Edge.Cuts segment of J3) vs (pad
# of J3) - the edge segment is item A, the pad is item B.
(rule "SP1 gold fingers - allow copper to board edge"
	(condition "A.memberOfFootprint('J3') || B.memberOfFootprint('J3')")
	(constraint edge_clearance (min -0.5mm)))

# Power-integrity: flag any power-rail track narrower than its netclass width.
# A netclass "track width" is only the DEFAULT for new routing - KiCad does NOT
# enforce it - so without these rules an under-width power trace passes DRC
# silently. These make DRC surface every thin power segment so they don't have to
# be found by eye. Severity is "warning" (not error) so an unavoidable neck into a
# fine-pitch pin is flagged for review but never blocks fab export.
(rule "Power rail minimum width (0.3mm)"
	(severity warning)
	(condition "A.NetClass == 'Power'")
	(constraint track_width (min 0.3mm)))

(rule "Low-current power rail minimum width (0.25mm)"
	(severity warning)
	(condition "A.NetClass == 'PowerLV'")
	(constraint track_width (min 0.25mm)))
