Moved all components to F.Cu
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# re-bba-rb — bring-up TODO / findings (first physical unit)
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Findings from bringing up the first assembled V1 board (repaired: 7 shorted
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vias drilled out, some collateral trace damage). Started 2026-08-23. This is a
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running list — items are **not** being worked yet, just recorded.
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## Established good so far (context)
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- Bitstream flashes + verifies (`iceprog`, channel A); FPGA configures (heartbeat).
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- FT2232H healthy (channel-A MPSSE + channel-B internal loopback both pass).
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- **W5100 clock confirmed GOOD** (Y2 25 MHz crystal oscillating): the on-board
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diagnostic (`scratchpad/w5100_check.py`) shows solid green — MR software-reset
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self-clears, which only happens on the internal clock.
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- W5100 register write/read-back works on 7 of 8 data lines.
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## Known damage on THIS unit (self-inflicted, from the via repair — not design bugs)
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- **UART_RXD trace broken** (FPGA pin 19 → FT2232H pin 39). Workaround built:
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`UART_J4=1` synth build relocates the UART to the J4 header (DBG0=pin9=TX,
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DBG1=pin10=RX, GND=J4 pin1) for an external USB-UART/Pi dongle.
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- **ETH_D3 trace broken** (W5100 data bit 3): net `ETH_D3` = FPGA **U9 pin 28**
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↔ W5100 **U11 pin 40**. Confirmed by the diagnostic's red blink-code (4 blinks
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= D3). One bodge needed; bridge the drilled break (scrape to trace copper / a
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via — no need to touch the 0.5 mm chip pads). Optional: remap the FPGA D3 bit
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to a spare J4 pad (DBG2=pin11=J4 pin4) to make one end a coarse header pad.
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---
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## TODO
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### 1. LED brightness — LED_G and the two transistor-driven LEDs are blindingly bright
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**Observation:** `LED_G` (D6, green) and the two transistor-driven LEDs are far
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too bright; `LED_R` (D7, red) is fine.
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**Root cause (from netlist):** the series resistors are wrong.
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- `LED_R` (D7, red): **R38 = 330 Ω** → correct brightness (the reference).
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- `LED_G` (D6, green): **R37 = 49.9 Ω** → ~25 mA, blinding.
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- Transistor-driven: **D8** (green, via Q1 S8050) and **D9** (green, via Q2
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S8550, collector → **R42 = 49.9 Ω** → D9) → same over-drive. (Confirm D8's
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own series resistor value too.)
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**Fix direction:** raise the 49.9 Ω LED series resistors (**R37**, **R42**, and
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D8's) to ~**330 Ω–1 kΩ** to match D7. (The 49.9 Ω value looks copy-pasted from
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the impedance-matching resistors — wrong part for an LED.) The RGB LED
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(D11/D12/D13 via `SB_RGBA_DRV`, `RGB*_CURRENT=0b000001`) is separate and not
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part of this complaint. BOM/PCB change for V2; a rework could tack larger
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resistors on this unit if the brightness is a bench nuisance.
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### 2. GC_ON is not the clean on/off the gateware assumed (sits at 2.3 V; both handover LEDs on)
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**Observation:** `GC_ON` measures **2.3 V** (not a clean rail). With **both USB
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and GC connected**, both transistor-driven LEDs (D8, D9) are lit — the intent
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was a power-handover indicator with only ever one active (USB vs GC).
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**Analysis (from netlist):** `GC_ON` = TPS2116 status (net: U2.8 = mux ST,
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U12.3, FPGA **U9 pin 21**, pulled up by R5 10 k to 3V3; drives Q1 base via R39
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10 k and Q2 base via R40 10 k). The two indicator transistors are complementary
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(Q1 = S8050 NPN, Q2 = S8550 PNP) expecting GC_ON to swing rail-to-rail:
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- At **GC_ON ≈ 2.3 V**, the NPN (Q1, on when base ≳0.7 V) **and** the PNP (Q2, on
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when base ≲2.6 V) **both conduct** → both D8 and D9 light. There is no clean
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one-or-the-other point at this intermediate voltage.
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**Two things to resolve:**
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- **Hardware:** the complementary-transistor indicator doesn't give a clean
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handover display at the actual GC_ON level. Re-think for V2 (e.g., a comparator
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/ proper level, or drive the two indicators from a real one-hot power-source
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signal). First confirm what GC_ON's ST pin actually does across the USB-only /
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GC-only / both states (TPS2116 ST semantics — see REVIEW.md).
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- **Gateware:** GC_ON is wired to FPGA pin 21 but **not yet used**. The planned
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"gate all outputs on GC_ON" (see TODO.md) assumed GC_ON is a clean logic level.
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2.3 V is above the iCE40 3.3 V-LVCMOS V_IH (~2.0 V) so pin 21 would read HIGH,
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but it's marginal and the semantics aren't the assumed on/off. Verify the real
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signal before relying on it for output gating.
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### 3. Functional W5100 test — send a packet capturable in Wireshark (works around broken D3?)
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**Goal:** a test bitstream that makes the W5100 transmit a frame on the wire,
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captured with Wireshark on the laptop (magjack J2 → laptop).
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**Feasible:** reuse `W5100ParallelMaster` (MACRAW socket 0, or the UDP socket
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path) with a small periodic trigger + a canned frame. Init runs on NCRA/startup.
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**Caveat — the broken ETH_D3:** every byte written to the W5100 has data bit 3
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corrupted, so a frame sent *now* would have wrong MAC/ethertype/payload bytes —
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Wireshark might see a malformed frame (or the W5100 may reject a bad length).
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- A garbled frame appearing at all would still prove **TX path + PHY + magnetics**
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work on the wire.
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- For a **clean, valid** packet capture, do the **ETH_D3 bodge first** (item in
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"Known damage"). Recommended order: bodge D3 → re-run `w5100_check` (red should
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go dark) → then this packet test.
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### 4. Bit-bang EXI from a Raspberry Pi to test the FPGA's EXI capture
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**Goal:** validate the EXI Mode-3 capture front-end without a GameCube, by having
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a Pi emulate the GC EXI master.
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**Approach:** Pi SPI **master, Mode 3 (CPOL=1, CPHA=1)**, 3.3 V (both sides
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3.3 V — no shifting). Drive the EXI **device-ID query** and check the response:
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write `0x0000` (2 bytes) then read 4 bytes → must be **`0x04 0x02 0x02 0x00`**.
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In SPI terms: assert CS, clock out `00 00 xx xx xx xx`, the last 4 MISO bytes are
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the device ID. A match proves ExiCapture → register file → MISO end-to-end.
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**Connections (FPGA EXI pins):** CLK=44, MOSI=4, MISO=3, CS=45 (INT=46) — reach
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them at the SP1 edge connector J3 or the damper resistors (R21/R25). Map to Pi:
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Pi SCLK→CLK, Pi MOSI→MOSI(FPGA in), Pi MISO←MISO(FPGA out), Pi CE→CS, GND↔GND.
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**Notes:** run the Pi SPI **slow** (e.g., 1 MHz) — the capture domain oversamples
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the EXI clock, so a slow clock is *easier* than the real 27 MHz and fully
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exercises the Mode-3 logic + register file. Good first EXI smoke test before
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trusting it against a real console.
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### 5. RGB LEDs (D11 red / D12 green / D13 yellow) — drive bug + brightness
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Two findings, from lighting them for the first time at bring-up:
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**(a) DRIVE BUG — they don't light in the current gateware (functional, not cosmetic).**
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`SB_RGBA_DRV`'s `o_RGB0/1/2` outputs are left as dangling internal signals in
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`synth.py` (and were in the first test builds). nextpnr never bonds them to the
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dedicated RGB pads (pins 39/40/41 — confirmed absent from the PCF), so the driver
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outputs float and **the LEDs never light**. This means the **rx / tx / ready RGB
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indicators are non-functional in the default build.**
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- **Fix (confirmed on the bench):** request the RGB pins *raw* (no SB_IO buffer)
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and connect the driver outputs directly to the pads:
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```python
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rgb = platform.request("rgbpad", 0, dir="-") # Resource: r=39 g=40 b=41
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Instance("SB_RGBA_DRV", ...,
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o_RGB0=rgb.r.io, o_RGB1=rgb.g.io, o_RGB2=rgb.b.io)
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```
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Connecting through a normal `dir="o"` request fails packing:
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`ERROR: SB_RGB_DRV/SB_RGBA_DRV port connected to more than just package pin!`
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- **APPLIED 2026-08-23** in `synth.py`: added a raw `rgb` Resource (39/40/41) and
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wired `o_RGB0/1/2 = rgb.{r,g,b}.io`; the RGB indicators now light.
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**(b) BRIGHTNESS — only GREEN (D12) is too bright; red (D11) and yellow (D13)
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are fine.** Measured with the corrected drive at the driver's *minimum* current
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(`CURRENT_MODE` half, `RGBx_CURRENT=0b000001`). The green die is much more
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efficient per mA, so at the same minimum current it's blinding while red/yellow
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look right. Since the current code is already at minimum, the fix is **PWM
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dimming on green only** — feed a low-duty PWM into `RGB1PWM` (green) instead of a
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static `1`, and leave red/yellow (`RGB0PWM`/`RGB2PWM`) driven solid.
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- **APPLIED 2026-08-23** in `synth.py`: a `_GRN_DUTY` (default 2/16 ≈ 1/8) PWM now
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gates **both** green emitters — `RGB1PWM` (D12) and `LED_G`/D6 (the discrete
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heartbeat, over-bright from R37 — item 1). Red/yellow/LED_R stay solid. Tune
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`_GRN_DUTY` (0..15) at the bench. Gateware mitigation; the proper V2 hardware
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fix for D6 is still R37 → ~330 Ω (item 1).
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### 6. (reserved — Dennis to add)
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_Placeholder for the item Dennis was trying to recall._
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@@ -0,0 +1,67 @@
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#!/usr/bin/env python3
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"""EXI device-ID query for re-bba-rb bring-up — run on a Raspberry Pi wired to
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the FPGA's EXI pins, to validate the GameCube-facing capture path with NO W5100
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involved (so it works even on a unit whose W5100/ethernet side is dead).
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It bit-bangs the EXI SPI the way the GameCube does: CLK idles HIGH; the FPGA
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samples MOSI on the falling edge and drives MISO on the rising edge. It sends
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the device-ID read header (read 4 bytes @ addr 0 = 0x00 0x03), then pauses (the
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GC pauses the clock between the header and the data so the FPGA can prefetch the
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response), then clocks read bytes and looks for the reply 04 02 02 00.
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Wiring (Pi BCM GPIO -> FPGA EXI, all 3.3 V, shared GND):
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CLK -> EXI CLK (FPGA pin 44)
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MOSI -> EXI MOSI (FPGA pin 4, an FPGA *input*)
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MISO <- EXI MISO (FPGA pin 3, an FPGA *output*)
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CS -> EXI CS (FPGA pin 45)
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GND <-> GND
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Reach these at the SP1 edge connector (J3) or on the series damper resistors.
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Edit the BCM pin numbers below to match your wiring. Run: sudo python3 exi_devid_rpi.py
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Requires the FPGA to be running the full BBA design (e.g. build/seed3/top.bin)
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and its 12 MHz clock (X1) alive — both independent of the W5100.
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"""
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import time
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try:
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import RPi.GPIO as GPIO
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except ImportError:
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raise SystemExit("needs RPi.GPIO -> sudo apt install python3-rpi.gpio")
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# ---- set these to your actual Pi BCM pin numbers ----
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CLK, MOSI, MISO, CS = 11, 10, 9, 8
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GPIO.setmode(GPIO.BCM)
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GPIO.setup(CLK, GPIO.OUT, initial=1) # CPOL=1: clock idles HIGH
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GPIO.setup(MOSI, GPIO.OUT, initial=0)
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GPIO.setup(CS, GPIO.OUT, initial=1) # inactive HIGH
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GPIO.setup(MISO, GPIO.IN)
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def xfer(b):
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"""Clock one byte MSB-first; FPGA samples MOSI on falling, drives MISO on rising."""
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r = 0
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for i in range(7, -1, -1):
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GPIO.output(MOSI, (b >> i) & 1) # MOSI stable while CLK is high
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GPIO.output(CLK, 0) # falling edge -> FPGA samples MOSI
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GPIO.output(CLK, 1) # rising edge -> FPGA drives MISO
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r = (r << 1) | GPIO.input(MISO)
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return r
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GPIO.output(CS, 0) # assert CS (active low)
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xfer(0x00) # header byte 0: read, addr[12:6]=0
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xfer(0x03) # header byte 1: addr[5:0]=0, len-1=3 (4 B)
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time.sleep(0.001) # gap so the FPGA can prefetch the reply
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resp = [xfer(0x00) for _ in range(6)] # clock a few read bytes
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GPIO.output(CS, 1) # deassert CS
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GPIO.cleanup()
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print("read bytes:", " ".join("%02x" % x for x in resp))
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want = [0x04, 0x02, 0x02, 0x00]
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found = any(resp[i:i + 4] == want for i in range(len(resp) - 3))
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if found:
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print("EXI device-ID 04 02 02 00 -> FOUND. EXI capture path works!")
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else:
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print("device-ID not found. Try: swap to mode-2 edges (move the MISO sample "
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"to just before the falling edge), check wiring/GND, confirm the FPGA "
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"is running the BBA design and its 12 MHz clock is alive.")
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+22159
-22479
File diff suppressed because it is too large
Load Diff
@@ -1,6 +1,6 @@
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{
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"board": {
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"active_layer": 2,
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"active_layer": 0,
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"active_layer_preset": "",
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"auto_track_width": true,
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"hidden_netclasses": [],
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@@ -1035,6 +1035,7 @@
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"netlist": "",
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"plot": "gerbers/",
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"specctra_dsn": "",
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"step": "",
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"vrml": ""
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},
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"page_layout_descr_file": ""
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