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fix(w5100): W5100S TX/RX buffer base is 0x8000/0xC000, not 0x4000/0x6000

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The W5100ParallelMaster used the original W5100's TX (0x4000) / RX (0x6000)
memory-block base addresses. This board's chip is a W5100S, whose TX/RX memory
blocks live at 0x8000 / 0xC000 (datasheet: TX 0x8000-0xBFFF, RX 0xC000-0xFFFF).

Consequence found at hardware bring-up (2026-09-20): every frame was written to
dead address space, so SEND transmitted the (empty) real TX buffer -- the chip
reported "sent" but nothing valid reached the wire (peer rx_packets stayed 0,
link up). The sim bus-model used these same constants, so it never caught it --
exactly the "register addresses are datasheet-from-memory, confirm at bring-up"
risk. All socket register offsets were verified correct against the W5100S
datasheet; only the two memory bases were wrong. Fixes both the socket-N UDP
test and the socket-0 MACRAW (GC) path.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
This commit is contained in:
Dennis Brentjes
2026-09-20 14:33:37 +00:00
parent c0c123e88b
commit 162dbf7d5f
1 changed files with 11 additions and 4 deletions
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exi_bba/w5100_parallel_master.py
+11 -4
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@@ -66,9 +66,16 @@ _S0_RX_RD = 0x0428 # Socket 0 RX read pointer
# Per-socket register/buffer geometry (2 KB per socket, RMSR/TMSR=0x55). # Per-socket register/buffer geometry (2 KB per socket, RMSR/TMSR=0x55).
# The UDP-test socket number is configurable; addresses are computed from it in # The UDP-test socket number is configurable; addresses are computed from it in
# __init__ (see _socket_addrs). Socket-n register block base = 0x0400+n*0x100, # __init__ (see _socket_addrs). Socket-n register block base = 0x0400+n*0x100,
# TX buffer base = 0x4000+n*0x800, RX buffer base = 0x6000+n*0x800. # TX buffer base = 0x8000+n*0x800, RX buffer base = 0xC000+n*0x800.
_TX_BASE = 0x4000 # Socket 0 TX buffer base (default 2 KB window) # ⚠️ The TX/RX MEMORY blocks live at 0x8000 / 0xC000 on the **W5100S** (this
_RX_BASE = 0x6000 # Socket 0 RX buffer base # board's chip) — NOT 0x4000 / 0x6000 as on the original W5100. Getting this
# wrong writes frames to dead address space: SEND then transmits the (empty)
# real TX buffer, so the chip reports "sent" but nothing valid reaches the wire
# (bench-confirmed at bring-up 2026-09-20 — rx_packets=0 on the peer). The sim
# bus-model used these same constants so it never caught it; confirmed against
# the W5100S datasheet (TX 0x8000-0xBFFF, RX 0xC000-0xFFFF).
_TX_BASE = 0x8000 # Socket 0 TX buffer base (W5100S)
_RX_BASE = 0xC000 # Socket 0 RX buffer base (W5100S)
_S0_TX_MASK = 0x07FF # 2 KB ring mask _S0_TX_MASK = 0x07FF # 2 KB ring mask
_S0_RX_MASK = 0x07FF _S0_RX_MASK = 0x07FF
_SN_MASK = 0x07FF # 2 KB ring mask (any socket) _SN_MASK = 0x07FF # 2 KB ring mask (any socket)
@@ -81,7 +88,7 @@ def _socket_addrs(n):
MR=base + 0x00, CR=base + 0x01, IR=base + 0x02, SR=base + 0x03, MR=base + 0x00, CR=base + 0x01, IR=base + 0x02, SR=base + 0x03,
PORT=base + 0x04, DIPR=base + 0x0C, DPORT=base + 0x10, PORT=base + 0x04, DIPR=base + 0x0C, DPORT=base + 0x10,
TX_WR=base + 0x24, RX_RSR=base + 0x26, RX_RD=base + 0x28, TX_WR=base + 0x24, RX_RSR=base + 0x26, RX_RD=base + 0x28,
TX_BASE=0x4000 + n * 0x0800, RX_BASE=0x6000 + n * 0x0800, TX_BASE=0x8000 + n * 0x0800, RX_BASE=0xC000 + n * 0x0800,
) )
# MR bits / command / mode values # MR bits / command / mode values