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schematic: eFuse OVLO ladder + ILIM fix (V2.1)

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Implements the values worked out in 6ce7657.

  R45  100k -> 33k    ILIM 0.52 A -> 1.52 A (clears the 621 mA inrush)
  R46  620k -> 150k   ladder R1: 12V_RAW -> EN/UVLO
  R47  100k -> 10k    ladder R2: EN/UVLO -> OVLO
  R48  NEW    12k  \  ladder R3 = 14.2k: OVLO -> GND
  R49  NEW    2.2k /
  U13 pin 2 (OVLO) taken off GND and onto the new EFUSE_OVLO net

Verified: netlist shows 12V_RAW(R46.1) / EFUSE_EN(R46.2,R47.1,U13.5) /
EFUSE_OVLO(R47.2,R48.1,U13.2) / EFUSE_R3MID(R48.2,R49.1) / GND(R49.2,R45.2,
U13.4); 150 -> 152 components with none dropped (the malformed-property trap
from the kicad-bom-edit skill); ERC 0 violations.

PCB placement and routing still to do.

Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
This commit is contained in:
Dennis Brentjes
2026-10-02 08:52:34 +00:00
parent 6ce7657f05
commit 228ff03cb6
2 changed files with 396 additions and 167 deletions
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hardware/re-bba-rb/TODO.md
+9 -3
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@@ -246,15 +246,21 @@ schematic changes.
the TPS25961 selects the internal *fixed* overvoltage cutoff ~5.98 V — so a
12 V rail is permanently in overvoltage lockout and the eFuse passes
nothing (bench-confirmed: 12V_EXI=0, GC_ON=0, W5100 unpowered).
**FIX WORKED OUT FROM THE DATASHEET 2026-10-02 — values final, needs
schematic + PCB work.** TI 3-resistor ladder (§8.2.3.2), EN/UVLO tapped at
**SCHEMATIC DONE 2026-10-02 (netlist + ERC verified) — PCB PLACEMENT
AND ROUTING STILL TO DO.** TI 3-resistor ladder (§8.2.3.2), EN/UVLO tapped at
R1–R2 and OVLO at R2–R3, plus an ILIM correction:
R46 620 k -> **150 k** (C93947) R1, top: 12V_RAW -> EN/UVLO
R47 100 k -> **10 k** (C25744) R2: EN/UVLO -> OVLO
R48 NEW -> **12 k** (C25752) \ R3 = 14.2 k in series,
R49 NEW -> **2.2 k** (C25879) / OVLO -> GND
R45 100 k -> **33 k** (C25779) ILIM 0.52 A -> 1.52 A
U13 pin 2 (OVLO): disconnect from GND, wire to the R47/R48 junction.
U13 pin 2 (OVLO): disconnected from GND, now on net EFUSE_OVLO.
Verified after the edit: nets are 12V_RAW(R46.1) / EFUSE_EN(R46.2, R47.1,
U13.5) / EFUSE_OVLO(R47.2, R48.1, U13.2) / EFUSE_R3MID(R48.2, R49.1) /
GND(R49.2, R45.2, U13.4); component count 150 -> 152 with nothing
dropped; ERC 0 violations. **PCB TODO:** place R48/R49 near U13, route
the new EFUSE_OVLO and EFUSE_R3MID nets, and re-export BOM + CPL
(reapplying CPL_ROTATIONS.md afterwards).
Gives UVLO 8.93 V typ (unchanged from today) and OVLO 15.21 V typ,
15.81 V worst case — under U3's 17 V input rating, which is what actually
caps the OVLO target. ILIM must exceed the board's own 621 mA inrush;