Rework the EXI decoder to the real GC<->BBA protocol
Replaces the invented 2-byte header (addr split across both bytes, 2-bit
length field) with the protocol libogc and Swiss actually speak:
command (bit7=0, 6-bit reg) [reg, 00, 00, data] one 4-byte transfer
register (bit7=1, 16-bit reg) [0x80|w<<6, ah, al, 00] + data until CS
This was not an optimisation: the old decoder read Swiss's NWAYS read
(80 00 31 00) as 'write 0x31 to NCRA', and bit 0 of 0x31 is RESET, so every
register read would have reset the device.
Changes:
* 16-bit address; no length field -- register reads and writes now stream
until CS, like the SPRAM path already did
* RHDR_LO starts the SPRAM fetch as soon as the address completes, using
the trailing header byte as the prefetch window the protocol provides
* command space serves EXI regs 0x02/0x03 (interrupt mask/status), the only
two Swiss uses
* EXI_GetID gets its own path: it offers just ONE header byte of warning, so
the first ID byte is pushed the instant byte 0 identifies the query
Two timing subtleties, both found by simulation and commented in place:
* MISO is driven LIVE from the tx FIFO head, so a byte pushed while the pad
byte is on the wire appears in the pad slot. A filler byte is parked
there (MISO is don't-care through the header) so the first real response
lands in data slot 0.
* the prefetch must be one-shot; re-firing while waiting for the pad byte
consumed the register stream early and shifted reads by a byte.
All testbenches updated to the real format and passing: bba_register_file
(7), bba_top (8 incl. the full W5100->SPRAM->GC loop and TX), exi_j4,
exi_capture, spi_mode3_slave, tx_frame_drain, spram_arbiter,
rx_frame_assembler, w5100_parallel_master. gc_bba_test rebuilt against the
new protocol.
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
This commit is contained in:
+230
-67
@@ -202,11 +202,24 @@ class BBARegisterFile(Elaboratable):
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m.d.comb += self.ncra_sr.eq(r_ncra[3]) # start-receive bit
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# ── Transaction state ────────────────────────────────────────────
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hdr0 = Signal(8)
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addr = Signal(13)
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# Real GC<->BBA header (see docs/exi_protocol_real.md), verified
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# against libogc and Swiss. Byte 0 bit7 selects the address space and
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# bit6 is the write flag; there is NO length field -- the data phase
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# runs until CS.
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# command (bit7=0): [reg&0x3F, 00, 00, data] one 4-byte transfer
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# register (bit7=1): [0x80|w<<6, ah, al, 00] + data phase until CS
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addr = Signal(16)
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is_write = Signal()
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xfer_len = Signal(2) # 0=1B … 3=4B
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byte_ctr = Signal(2)
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cmd_space = Signal() # this transaction is a command access
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cmd_reg = Signal(6)
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byte_ctr = Signal(3) # response-byte index (device-ID sequence)
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cmd_wr = Signal() # command-space write pending
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prefetched = Signal() # first response byte already pushed
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cmd_wdata = Signal(8)
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# EXI-side command registers. Swiss uses exactly two: 0x02 is the EXI
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# interrupt mask and 0x03 the EXI interrupt status (write-1-to-clear).
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r_cmd_imr = Signal(8)
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r_cmd_ir = Signal(8)
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tx_frame_len = Signal(16)
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# TX trigger bookkeeping. `twd_armed` fires one cycle AFTER TWD_HI is
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# written, so tx_frame_len has both halves by then; `tx_queued` records
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@@ -226,7 +239,7 @@ class BBARegisterFile(Elaboratable):
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# sp_addr — next SPRAM byte address to request (auto-increments)
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# outstanding — SPRAM requests issued but whose responses are not yet
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# popped (bounds prefetch and is drained at end)
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sp_addr = Signal(13)
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sp_addr = Signal(16)
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outstanding = Signal(4)
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SP_LIMIT = 4 # max prefetch depth in flight
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@@ -234,7 +247,7 @@ class BBARegisterFile(Elaboratable):
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# pointer (set to the base in HEADER1, incremented per byte). Keeping
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# it registered keeps the 13-bit adder off the combinational path that
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# feeds the read-response mux → tx_fifo write data.
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eff_addr = Signal(13)
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eff_addr = Signal(16)
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rd_sel = eff_addr[0:8]
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# ── Combinational read-response value (non-SPRAM) ────────────────
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@@ -259,11 +272,17 @@ class BBARegisterFile(Elaboratable):
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with m.Case(0): m.d.comb += devid.eq(0x04)
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with m.Case(1): m.d.comb += devid.eq(0x02)
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with m.Case(2): m.d.comb += devid.eq(0x02)
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with m.Case(3): m.d.comb += devid.eq(0x00)
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with m.Default(): m.d.comb += devid.eq(0x00)
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cmd_rdval = Signal(8)
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with m.Switch(cmd_reg):
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with m.Case(0x02): m.d.comb += cmd_rdval.eq(r_cmd_imr)
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with m.Case(0x03): m.d.comb += cmd_rdval.eq(r_cmd_ir)
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with m.Default(): m.d.comb += cmd_rdval.eq(0)
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rd_val = Signal(8) # response for the current non-SPRAM read byte
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with m.If((addr == 0) & id_phase):
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m.d.comb += rd_val.eq(devid)
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with m.If(cmd_space):
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m.d.comb += rd_val.eq(cmd_rdval)
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with m.Else():
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m.d.comb += rd_val.eq(reg_rdval)
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@@ -292,35 +311,132 @@ class BBARegisterFile(Elaboratable):
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with m.FSM(domain="exi", name="exi_fsm"):
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with m.State("HEADER0"):
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# Byte 0 selects the space and direction. The REAL protocol
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# (docs/exi_protocol_real.md) has no length field: the GC
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# clocks as many data bytes as it wants and ends with CS.
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with m.If(self.rx_rdy):
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m.d.comb += self.rx_en.eq(1)
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m.d.exi += hdr0.eq(self.rx_data)
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m.next = "HEADER1"
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m.d.exi += [is_write.eq(self.rx_data[6]), prefetched.eq(0),
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byte_ctr.eq(0), sp_req.eq(0), outstanding.eq(0)]
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with m.If(self.rx_data[7]): # register space
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m.d.exi += cmd_space.eq(0)
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m.next = "RHDR_HI"
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with m.Else(): # command space
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m.d.exi += [cmd_space.eq(1),
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cmd_reg.eq(self.rx_data[0:6]),
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addr.eq(self.rx_data[0:6]),
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eff_addr.eq(self.rx_data[0:6])]
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# EXI_GetID (byte 0 == 0x00) gives only ONE header
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# byte of warning before the GC starts clocking the
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# reply, so push the first ID byte the instant byte 0
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# identifies the query -- the earliest point possible.
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with m.If((self.rx_data == 0x00) & id_phase
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& self.tx_rdy):
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m.d.comb += [self.tx_data.eq(0x04), self.tx_en.eq(1)]
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m.d.exi += byte_ctr.eq(1)
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m.next = "CHDR_1"
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with m.State("HEADER1"):
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# ── register space: [0x80|w<<6, ah, al, 0x00] ──────────────────
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with m.State("RHDR_HI"):
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with m.If(self.rx_rdy):
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m.d.comb += self.rx_en.eq(1)
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new_addr = Cat(self.rx_data[2:8], hdr0[0:7]) # 13-bit addr
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new_len = self.rx_data[0:2]
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new_write = hdr0[7]
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m.d.exi += addr[8:16].eq(self.rx_data)
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m.next = "RHDR_LO"
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m.d.exi += addr.eq(new_addr)
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m.d.exi += eff_addr.eq(new_addr) # running pointer init
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m.d.exi += xfer_len.eq(new_len)
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m.d.exi += is_write.eq(new_write)
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m.d.exi += byte_ctr.eq(0)
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m.d.exi += sp_req.eq(0)
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m.d.exi += drain_ctr.eq(0)
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with m.State("RHDR_LO"):
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# The address completes HERE, one whole byte before the data
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# phase. That trailing 0x00 byte is the device's prefetch
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# window -- the old 2-byte-plus-length format spent those bits
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# on the length field and left zero slack, which is why the
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# first on-console read came back 22 bit-times late. Kick the
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# fetch off now so the answer is ready for the first data slot.
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with m.If(self.rx_rdy):
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m.d.comb += self.rx_en.eq(1)
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full = Cat(self.rx_data, addr[8:16]) # 16-bit address
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m.d.exi += [addr.eq(full), eff_addr.eq(full),
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sp_addr.eq(full)]
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with m.If(~is_write & (full >= 0x100) & spram_req.w_rdy):
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m.d.exi += [spram_req.w_data.eq(full),
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spram_req.w_en.eq(1),
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sp_addr.eq(full + 1),
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outstanding.eq(1)]
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# MISO is driven LIVE from the tx FIFO head, so a byte
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# pushed now would show up during the pad slot rather than
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# the first data slot. Park a filler byte there -- MISO is
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# don't-care for the whole header -- so the real first
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# response byte lands one slot later, where it belongs.
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with m.If(~is_write & self.tx_rdy):
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m.d.comb += [self.tx_data.eq(0x00), self.tx_en.eq(1)]
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m.next = "RHDR_PAD"
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with m.If(new_write):
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with m.State("RHDR_PAD"):
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# Trailing header byte. For a register read, push the first
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# response byte during this byte-time so it has crossed the
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# tx CDC before the GC clocks data slot 0.
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with m.If(self.rx_rdy):
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m.d.comb += self.rx_en.eq(1)
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with m.If(is_write):
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m.next = "WRITE"
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with m.Elif(new_addr >= 0x100):
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# SPRAM region: stream until CS deasserts (DMA-capable).
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m.d.exi += sp_addr.eq(new_addr)
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m.d.exi += outstanding.eq(0)
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with m.Elif(addr >= 0x100):
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m.next = "SPRAM_STREAM"
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with m.Else():
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m.next = "REG_READ"
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with m.Elif(~is_write & (addr < 0x100) & self.tx_rdy & ~prefetched):
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# Prefetch the FIRST response byte (once!) while the pad
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# byte is still on the wire, so it has crossed the tx CDC
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# before the GC clocks data slot 0. Must be one-shot: this
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# branch is re-evaluated every cycle the pad byte has not
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# arrived, and repeating it would consume the register
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# stream early (symptom: reads shifted by a byte).
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m.d.comb += [self.tx_data.eq(rd_val), self.tx_en.eq(1)]
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m.d.exi += [eff_addr.eq(eff_addr + 1), prefetched.eq(1)]
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# ── command space: [reg, 00, 00, data] in ONE 4-byte transfer ──
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with m.State("CHDR_1"):
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with m.If(self.rx_rdy):
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m.d.comb += self.rx_en.eq(1)
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# EXI_GetID is its own shape: the GC writes 0x0000 (two
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# bytes, so it lands here as command reg 0) and then clocks
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# FOUR read bytes. Hand it the ID stream rather than the
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# single-byte command response.
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with m.If(~is_write & (cmd_reg == 0) & id_phase):
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# byte_ctr is NOT reset here: HEADER0 already pushed
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# ID byte 0 and advanced it. Resetting would restart
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# the sequence and duplicate the first byte.
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m.next = "DEVID"
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with m.Else():
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m.next = "CHDR_2"
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with m.Elif(~is_write & (cmd_reg == 0) & id_phase & self.tx_rdy):
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# Device-ID query: keep feeding the ID while byte 1 is
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# still on the wire so the tx FIFO stays ahead of the GC.
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# NOT one-shot -- the FIFO is only 2 deep, and stopping
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# after one byte leaves a hole in the next slot.
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m.d.comb += [self.tx_data.eq(devid), self.tx_en.eq(1)]
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m.d.exi += byte_ctr.eq(byte_ctr + 1)
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with m.Elif(~is_write & self.tx_rdy & ~prefetched):
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# Ordinary command read: response lands in byte slot 3.
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m.d.comb += [self.tx_data.eq(rd_val), self.tx_en.eq(1)]
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m.d.exi += prefetched.eq(1)
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with m.State("CHDR_2"):
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with m.If(self.rx_rdy):
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m.d.comb += self.rx_en.eq(1)
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m.next = "CHDR_3"
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with m.State("CHDR_3"):
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with m.If(self.rx_rdy):
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m.d.comb += self.rx_en.eq(1)
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with m.If(is_write):
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m.d.exi += cmd_wr.eq(1) # applied below
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m.d.exi += cmd_wdata.eq(self.rx_data)
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m.next = "TRAILER"
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with m.State("TRAILER"):
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# Soak up anything else the GC clocks, then wait for CS to rise.
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with m.If(self.rx_rdy):
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m.d.comb += self.rx_en.eq(1)
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with m.If(~self.cs_active):
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m.next = "HEADER0"
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with m.State("WRITE"):
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# Consume xfer_len+1 data bytes, writing the register file.
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@@ -374,32 +490,32 @@ class BBARegisterFile(Elaboratable):
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m.d.exi += tx_bytes.w_en.eq(1)
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# All other addresses silently ignored
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with m.If(byte_ctr == xfer_len):
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m.next = "HEADER0"
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with m.Else():
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m.d.exi += byte_ctr.eq(byte_ctr + 1)
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m.d.exi += eff_addr.eq(eff_addr + 1)
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# No length field in the real protocol: consume data
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# bytes until CS rises.
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m.d.exi += eff_addr.eq(eff_addr + 1)
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with m.If(~self.cs_active):
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m.next = "HEADER0"
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with m.State("REG_READ"):
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# Register / device-ID read (addr < 0x100): value available
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# immediately, bounded by the header's xfer_len (≤4 bytes).
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with m.If(self.tx_rdy):
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m.d.comb += self.tx_data.eq(rd_val)
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m.d.comb += self.tx_en.eq(1)
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with m.If(byte_ctr == xfer_len):
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m.next = "READ_DRAIN"
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with m.Else():
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m.d.exi += byte_ctr.eq(byte_ctr + 1)
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m.d.exi += eff_addr.eq(eff_addr + 1)
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# Register read (addr < 0x100): stream until CS, like the SPRAM
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# path. The real protocol has no length field.
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with m.If(self.tx_rdy & self.cs_active):
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m.d.comb += [self.tx_data.eq(rd_val), self.tx_en.eq(1)]
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m.d.exi += eff_addr.eq(eff_addr + 1)
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with m.If(self.rx_rdy):
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m.d.comb += self.rx_en.eq(1) # drain dummies
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with m.If(~self.cs_active):
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m.next = "HEADER0"
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with m.State("READ_DRAIN"):
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# Discard the xfer_len+1 dummy bytes the GC clocks while reading.
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with m.State("DEVID"):
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# Stream 04 02 02 00 until CS rises.
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with m.If(self.tx_rdy & self.cs_active):
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m.d.comb += [self.tx_data.eq(devid), self.tx_en.eq(1)]
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m.d.exi += byte_ctr.eq(byte_ctr + 1)
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with m.If(self.rx_rdy):
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m.d.comb += self.rx_en.eq(1)
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with m.If(drain_ctr == xfer_len):
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m.next = "HEADER0"
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with m.Else():
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m.d.exi += drain_ctr.eq(drain_ctr + 1)
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with m.If(~self.cs_active):
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m.next = "HEADER0"
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with m.State("SPRAM_STREAM"):
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# Stream SPRAM bytes until CS deasserts — handles both ≤4-byte
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@@ -441,6 +557,13 @@ class BBARegisterFile(Elaboratable):
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with m.If((outstanding == 0) & ~self.rx_rdy & ~spram_rsp.r_rdy):
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m.next = "HEADER0"
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# ── Command-space write, applied the cycle after CHDR_3 ──────────
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with m.If(cmd_wr):
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m.d.exi += cmd_wr.eq(0)
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with m.Switch(cmd_reg):
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with m.Case(0x02): m.d.exi += r_cmd_imr.eq(cmd_wdata)
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with m.Case(0x03): m.d.exi += r_cmd_ir.eq(r_cmd_ir & ~cmd_wdata)
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# ── Interrupt output ─────────────────────────────────────────────
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m.d.exi += self.exi_int_n.eq(~(r_ir & r_imr).any())
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@@ -481,45 +604,81 @@ if __name__ == "__main__":
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# Drive the byte-stream interface directly (the SPI bit cadence and FIFOs
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# live in ExiCapture; here we model the byte producer/consumer).
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# Responses can be pushed WHILE the header is still being clocked -- the
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# device prefetches during the header's turnaround byte, and the device-ID
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# reply starts from header byte 0. So every helper that advances time has
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# to record tx pushes, or the early ones are silently lost and reads look
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# shifted. tx_log is that shared record; collect_tx drains it first.
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tx_log = []
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def sample_tx(ctx):
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if ctx.get(reg.tx_en):
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tx_log.append(ctx.get(reg.tx_data))
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async def push_rx(ctx, b):
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"""Present one received byte and wait for the register file to pop it."""
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ctx.set(reg.rx_data, b)
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ctx.set(reg.rx_rdy, 1)
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while True:
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en = ctx.get(reg.rx_en)
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sample_tx(ctx)
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await ctx.tick("exi")
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if en:
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break
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ctx.set(reg.rx_rdy, 0)
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async def collect_tx(ctx, n):
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"""Collect n response bytes pushed by the register file (bounded)."""
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"""Collect n response bytes, including any pushed during the header."""
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out = []
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while tx_log and len(out) < n:
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out.append(tx_log.pop(0))
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for _ in range(3000):
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if ctx.get(reg.tx_en):
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out.append(ctx.get(reg.tx_data))
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if len(out) >= n:
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break
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if ctx.get(reg.tx_en):
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out.append(ctx.get(reg.tx_data))
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await ctx.tick("exi")
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return out
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# Real protocol (docs/exi_protocol_real.md): register space is a 4-byte
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# header [0x80|w<<6, ah, al, 0x00] followed by a data phase that runs
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# until CS rises -- there is no length field.
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async def exi_read(ctx, addr, length=1):
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hdr0 = (addr >> 6) & 0x7F
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hdr1 = ((addr & 0x3F) << 2) | (length - 1)
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await push_rx(ctx, hdr0)
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await push_rx(ctx, hdr1)
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||||
result = await collect_tx(ctx, length) # READ pushes `length` bytes
|
||||
for _ in range(length): # READ_DRAIN dummies
|
||||
await push_rx(ctx, 0x00)
|
||||
tx_log.clear()
|
||||
ctx.set(reg.cs_active, 1)
|
||||
await push_rx(ctx, 0x80)
|
||||
await push_rx(ctx, (addr >> 8) & 0xFF)
|
||||
await push_rx(ctx, addr & 0xFF)
|
||||
await push_rx(ctx, 0x00) # turnaround / prefetch window
|
||||
# The device parks a filler byte in the pad slot (MISO is don't-care
|
||||
# for the whole header) so the first REAL response byte lands in data
|
||||
# slot 0. This bench counts pushes rather than wire slots, so drop it.
|
||||
result = (await collect_tx(ctx, length + 1))[1:]
|
||||
ctx.set(reg.cs_active, 0)
|
||||
await ctx.tick("exi").repeat(6)
|
||||
return result
|
||||
|
||||
async def exi_write(ctx, addr, data):
|
||||
hdr0 = 0x80 | ((addr >> 6) & 0x7F)
|
||||
hdr1 = ((addr & 0x3F) << 2) | (len(data) - 1)
|
||||
await push_rx(ctx, hdr0)
|
||||
await push_rx(ctx, hdr1)
|
||||
ctx.set(reg.cs_active, 1)
|
||||
await push_rx(ctx, 0xC0)
|
||||
await push_rx(ctx, (addr >> 8) & 0xFF)
|
||||
await push_rx(ctx, addr & 0xFF)
|
||||
await push_rx(ctx, 0x00)
|
||||
for b in data:
|
||||
await push_rx(ctx, b)
|
||||
ctx.set(reg.cs_active, 0)
|
||||
await ctx.tick("exi").repeat(6)
|
||||
|
||||
async def exi_devid(ctx):
|
||||
"""EXI_GetID: write 0x0000 (2 bytes), then clock 4 read bytes."""
|
||||
tx_log.clear()
|
||||
ctx.set(reg.cs_active, 1)
|
||||
await push_rx(ctx, 0x00) # command space, reg 0, read
|
||||
await push_rx(ctx, 0x00)
|
||||
result = await collect_tx(ctx, 4)
|
||||
ctx.set(reg.cs_active, 0)
|
||||
await ctx.tick("exi").repeat(6)
|
||||
return result
|
||||
|
||||
# SPRAM contents the streaming-read test reads back (byte i = 0xA0+i).
|
||||
spram_mem = {0x100 + i: (0xA0 + i) & 0xFF for i in range(64)}
|
||||
@@ -555,7 +714,7 @@ if __name__ == "__main__":
|
||||
await ctx.tick("exi").repeat(8)
|
||||
|
||||
# T1: Device ID (addr=0, 4-byte read)
|
||||
result = await exi_read(ctx, 0x0000, length=4)
|
||||
result = await exi_devid(ctx)
|
||||
if result != _DEVICE_ID:
|
||||
errors.append(f"T1 device ID: expected {_DEVICE_ID}, got {result}")
|
||||
print(f"T1 device ID: {[f'0x{b:02X}' for b in result]}")
|
||||
@@ -602,12 +761,16 @@ if __name__ == "__main__":
|
||||
errors.append(f"T5 INT_N after clear: expected 1, got {int_n}")
|
||||
print(f"T5 INT_N after IR clear: {int_n} (want 1)")
|
||||
|
||||
# T6: streaming SPRAM read (DMA) — read N>4 bytes from 0x100 by holding
|
||||
# cs_active and clocking past the header's 4-byte length field.
|
||||
# T6: streaming SPRAM read (DMA) — the real protocol has no length
|
||||
# field, so the data phase simply runs for as long as CS is held.
|
||||
# Swiss reads the packet buffer exactly this way (bba_ins -> DMA).
|
||||
N = 12
|
||||
tx_log.clear()
|
||||
ctx.set(reg.cs_active, 1)
|
||||
await push_rx(ctx, 0x04) # hdr0 → addr[12:6]; addr 0x100, read
|
||||
await push_rx(ctx, 0x00) # hdr1 → addr[5:0]=0, len field ignored
|
||||
await push_rx(ctx, 0x80) # register space, read
|
||||
await push_rx(ctx, 0x01) # addr[15:8] -> 0x0100
|
||||
await push_rx(ctx, 0x00) # addr[7:0]
|
||||
await push_rx(ctx, 0x00) # turnaround byte
|
||||
got = []
|
||||
for _ in range(5000):
|
||||
if ctx.get(reg.tx_en):
|
||||
|
||||
Reference in New Issue
Block a user