EXI bring-up: full Swiss init runs on hardware; W5100 TX blocked
The whole GC init sequence now runs over EXI on the real board: device ID, NCRA reset self-clear, PAR0-5, MAR, ANALOG, NWAYC, IMR, NCRA SR, NWAYS 0x17. GC->wire TX does not complete. Not an EXI fault and not tx_bytes depth -- 8-byte frames fail too, and the UART shell's own UDP send hangs the same way, so the W5100 bus master is stuck and TXFrameDrain is waiting on it. Also records that id_phase is a one-shot cleared by the first NCRA reset, so a re-run probe reads 00 00 00 00 for the device ID and looks broken. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
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#!/usr/bin/env python3
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"""Full BBA path test: Swiss init, GC->wire TX, wire->GC RX.
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Sends a broadcast ARP request ("who has 10.0.0.50, tell 10.0.0.99"). The PC
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should answer, which exercises the RX half in the same shot.
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"""
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import time, sys
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import RPi.GPIO as GPIO
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CLK, MOSI, MISO, CS = 11, 10, 9, 8
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GPIO.setmode(GPIO.BCM); GPIO.setwarnings(False)
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GPIO.setup(CLK, GPIO.OUT, initial=1); GPIO.setup(MOSI, GPIO.OUT, initial=0)
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GPIO.setup(CS, GPIO.OUT, initial=1); GPIO.setup(MISO, GPIO.IN)
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def xfer(b):
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r = 0
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for i in range(7, -1, -1):
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GPIO.output(MOSI, (b >> i) & 1)
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GPIO.output(CLK, 0)
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r = (r << 1) | GPIO.input(MISO)
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GPIO.output(CLK, 1)
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return r
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def read(addr, n):
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GPIO.output(CS, 0); GPIO.output(CLK, 1); time.sleep(0.0003)
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xfer((addr >> 6) & 0x7F); xfer(((addr & 0x3F) << 2) | ((n - 1) & 3))
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time.sleep(0.002)
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out = [xfer(0) for _ in range(n)] # EXACTLY n
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GPIO.output(CS, 1); time.sleep(0.0005)
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return out
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def write(addr, data):
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GPIO.output(CS, 0); GPIO.output(CLK, 1); time.sleep(0.0003)
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xfer(0x80 | ((addr >> 6) & 0x7F))
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xfer(((addr & 0x3F) << 2) | ((len(data) - 1) & 3))
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for b in data: xfer(b)
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GPIO.output(CS, 1); time.sleep(0.0005)
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def stream(addr, n):
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"""SPRAM/DMA read: addr >= 0x100 streams until CS, so clock freely."""
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GPIO.output(CS, 0); GPIO.output(CLK, 1); time.sleep(0.0003)
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xfer((addr >> 6) & 0x7F); xfer(((addr & 0x3F) << 2) | 3)
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time.sleep(0.002)
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out = [xfer(0) for _ in range(n)]
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GPIO.output(CS, 1); time.sleep(0.0005)
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return out
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def hx(v): return " ".join("%02x" % x for x in v)
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MAC = [0x00, 0x09, 0xBF, 0x00, 0x00, 0x01]
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SRC_IP, DST_IP = [10, 0, 0, 99], [10, 0, 0, 50]
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print("=" * 62)
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print("PHASE 1 Swiss init sequence")
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print("=" * 62)
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dev = read(0x0000, 4)
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print(f" 1. device ID {hx(dev)} {'OK' if dev==[4,2,2,0] else 'FAIL'}")
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if dev != [4, 2, 2, 0]:
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print(" (ID is a one-shot before the first NCRA reset - continuing)")
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write(0x00, [0x01]); print(" 2. NCRA = 0x01 (reset + W5100 init)")
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for i in range(40):
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v = read(0x00, 1)[0]
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if not (v & 1): print(f" 3. NCRA reset self-cleared after {i} polls"); break
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time.sleep(0.005)
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else:
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print(" 3. NCRA reset did NOT clear")
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write(0x20, MAC[:4]); write(0x24, MAC[4:])
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print(f" 4. PAR0-5 = {hx(read(0x20,4))} {hx(read(0x24,2))}")
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write(0x26, [0xFF]*4); write(0x2A, [0xFF]*4); print(" 5. MAR0-7 = FF (promiscuous multicast)")
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write(0x2E, [0xD6]); print(" 6. ANALOG = 0xD6")
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write(0x30, [0x01]); print(" 7. NWAYC")
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write(0x08, [0x86]); print(f" 8. IMR = 0x86, readback {hx(read(0x08,1))}")
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write(0x32, [0x02]); print(" 9. GCA")
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write(0x00, [0x08]); print(f" 10. NCRA SR=1, readback {hx(read(0x00,1))}")
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nw = read(0x31, 1); print(f" 11. NWAYS = {hx(nw)} {'link up' if nw==[0x17] else 'UNEXPECTED'}")
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# ---------------- build the ARP frame ----------------
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frame = [0xFF]*6 + MAC + [0x08, 0x06]
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frame += [0x00,0x01, 0x08,0x00, 0x06, 0x04, 0x00,0x01]
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frame += MAC + SRC_IP + [0x00]*6 + DST_IP
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frame += [0x00] * (60 - len(frame))
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print()
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print("=" * 62)
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print(f"PHASE 2 GC -> wire: {len(frame)}-byte broadcast ARP")
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print("=" * 62)
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print(f" who has {'.'.join(map(str,DST_IP))}, tell {'.'.join(map(str,SRC_IP))}")
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print(f" src MAC {':'.join('%02x'%b for b in MAC)}")
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rwp_before = read(0x16, 2)
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write(0x34, [len(frame) & 0xFF]); write(0x35, [(len(frame) >> 8) & 0xFF])
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print(f" TWD = {hx(read(0x34,2))} (frame length)")
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t0 = time.time()
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for b in frame:
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write(0x48, [b]) # one byte per transaction: eff_addr increments
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print(f" streamed {len(frame)} bytes to TXDATA in {time.time()-t0:.2f}s")
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write(0x00, [0x08 | 0x02]) # SR + ST0 -> TX trigger
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print(" NCRA ST set -> TX triggered")
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for i in range(30):
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ir = read(0x09, 1)[0]
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if ir & 0x04:
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print(f" IR = {ir:02x} TI (transmit complete) SET after {i} polls"); break
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time.sleep(0.01)
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else:
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print(f" IR = {read(0x09,1)[0]:02x} TI never set")
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print()
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print("=" * 62)
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print("PHASE 3 wire -> GC: waiting for the ARP reply")
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print("=" * 62)
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print(f" RWP before = {hx(rwp_before)}")
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got = None
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for i in range(60):
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rwp = read(0x16, 2)
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ir = read(0x09, 1)[0]
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if rwp != rwp_before or (ir & 0x02):
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got = (rwp, ir); break
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time.sleep(0.05)
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if got:
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rwp, ir = got
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print(f" RWP moved to {hx(rwp)}, IR = {ir:02x} (RI {'set' if ir&2 else 'clear'})")
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data = stream(0x0100, 80)
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print(f" SPRAM @0x100: {hx(data[:16])}")
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print(f" {hx(data[16:32])}")
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print(f" {hx(data[32:48])}")
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if 0x08 in data and 0x06 in data:
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print(" -> looks like an ARP frame came back. RX PATH WORKS.")
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else:
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print(f" no RX after 3s (RWP still {hx(read(0x16,2))}, IR {read(0x09,1)[0]:02x})")
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print(" TX may still have worked - check the capture.")
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GPIO.cleanup()
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