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Reworks the board further

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This commit is contained in:
Dennis Brentjes
2026-08-28 17:17:54 +02:00
parent 009a643698
commit 34c54d68b0
14 changed files with 38877 additions and 7103 deletions
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hardware/re-bba-rb/re-bba-rb.kicad_dru
+19 -16
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@@ -9,6 +9,18 @@
(condition "A.memberOfFootprint('J3') || B.memberOfFootprint('J3')")
(constraint edge_clearance (min -0.5mm)))
# Reverse-mount LED light-windows (D6/D7/D8/D9/D11/D12/D13, Everlight 24-21).
# Each footprint has an Edge.Cuts light-window cutout under the LED body; the
# datasheet land places the solder pads ~0.15mm from that cutout - below the
# JLCPCB 0.3mm copper-to-edge default, but the intended, manufacturer-recommended
# geometry (the copper sits under the part, not exposed). Relax edge_clearance to
# 0.1mm for these footprints so the deliberate geometry doesn't spam DRC, while
# still catching a genuinely-too-tight future edit (<0.1mm). Test BOTH items: the
# violated pair is (pad) vs (the footprint's own Edge.Cuts window segment).
(rule "Reverse-mount LED light-window - allow pad-to-cutout clearance"
(condition "A.memberOfFootprint('D6') || A.memberOfFootprint('D7') || A.memberOfFootprint('D8') || A.memberOfFootprint('D9') || A.memberOfFootprint('D11') || A.memberOfFootprint('D12') || A.memberOfFootprint('D13') || B.memberOfFootprint('D6') || B.memberOfFootprint('D7') || B.memberOfFootprint('D8') || B.memberOfFootprint('D9') || B.memberOfFootprint('D11') || B.memberOfFootprint('D12') || B.memberOfFootprint('D13')")
(constraint edge_clearance (min 0.1mm)))
# Power-integrity: flag any power-rail track narrower than its netclass width.
# A netclass "track width" is only the DEFAULT for new routing - KiCad does NOT
# enforce it - so without these rules an under-width power trace passes DRC
@@ -124,22 +136,13 @@
# it's the one thing the routing was actually for.
# USB_DP: 0.25mm width / 0.15mm gap -> ~91ohm (target 90ohm +/-15%)
# ETH_DP: 0.20mm width / 0.14mm gap -> ~100ohm (target 100ohm +/-15%)
# track_width keeps a +/-0.02mm max band (routing precision). diff_pair_gap
# has NO max: a max bound sounds right but false-flags normal pad fanout,
# where P/N necessarily diverge for a few mm right at the pad before
# converging into the coupled run - DRC can't tell that apart from a
# genuinely uncoupled long run, and real routing hit gaps of 0.65-1.65mm on
# fanout stubs vs a ~0.16mm max here. min still catches the case that matters
# (traces routed too close, i.e. below the fab clearance floor); max on gap
# only matters over a long uncoupled run, which is a length-matching/loss
# question, not something this board-wide rule can safely judge per-segment.
#
# Covers both halves of the D1/D4/D5 split-net TVS pattern: USB_DP now
# matches FT_DP/FT_DN (D1's chip-side pins) alongside USB_D+/USB_D-, and
# ETH_DP matches PHY_TX_P/PHY_TX_N/PHY_RX_P/PHY_RX_N (D4/D5's chip-side pins)
# alongside ETH_TX_P/N and ETH_RX_P/N - see netclass_patterns in
# re-bba-rb.kicad_pro. Without that, the chip-side half of each pair falls
# back to Default and silently skips the impedance target.
# track_width +/-0.02mm tolerance bands are routing precision, not re-derived
# targets. diff_pair_gap has a min (catches traces routed too close, below fab
# clearance) and opt, but intentionally NO max: a gap-max false-flags normal pad
# fanout, where P/N necessarily diverge over a sub-mm stub right at the pads
# before converging into the coupled run - KiCad can't tell that apart from a
# genuinely uncoupled long run (a length-matching/loss question, not one this
# board-wide per-segment rule can judge). Do NOT re-add a diff_pair_gap max.
(rule "USB differential pair width/gap (target ~90ohm)"
(severity error)