Finished the PCB design
This commit is contained in:
@@ -0,0 +1,242 @@
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(uuid "827fb795-2288-4955-ba83-dfe2c3abc6f8")
|
||||
)
|
||||
(pin "6"
|
||||
(uuid "02e0205b-86c9-4e57-a823-356fa0c37f0f")
|
||||
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|
||||
(pin "7"
|
||||
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|
||||
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|
||||
(instances
|
||||
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|
||||
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|
||||
(reference "D2")
|
||||
(unit 1)
|
||||
)
|
||||
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|
||||
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|
||||
)
|
||||
(symbol
|
||||
(lib_id "power:PWR_FLAG")
|
||||
(at 62.23 91.44 0)
|
||||
@@ -1749,6 +2394,81 @@
|
||||
)
|
||||
)
|
||||
)
|
||||
(symbol
|
||||
(lib_id "power:GND")
|
||||
(at 54.61 86.36 0)
|
||||
(unit 1)
|
||||
(body_style 1)
|
||||
(exclude_from_sim no)
|
||||
(in_bom yes)
|
||||
(on_board yes)
|
||||
(in_pos_files yes)
|
||||
(dnp no)
|
||||
(uuid "48052d59-dcf9-4791-9862-00c7a87de3b8")
|
||||
(property "Reference" "#PWR0tvs12v01"
|
||||
(at 58.42 86.36 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
)
|
||||
(property "Value" "GND"
|
||||
(at 55.372 86.36 0)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
(property "Footprint" ""
|
||||
(at 54.61 86.36 0)
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
(property "Datasheet" ""
|
||||
(at 54.61 86.36 0)
|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
)
|
||||
(property "Description" "Power symbol creates a global label with name \"GND\" , ground"
|
||||
(at 54.61 86.36 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
(effects
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(instances
|
||||
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|
||||
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|
||||
(reference "#PWR0tvs12v01")
|
||||
(unit 1)
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
(symbol
|
||||
(lib_id "power:GND")
|
||||
(at 74.93 101.6 90)
|
||||
@@ -1824,6 +2544,81 @@
|
||||
)
|
||||
)
|
||||
)
|
||||
(symbol
|
||||
(lib_id "power:GND")
|
||||
(at 38.1 105.41 0)
|
||||
(unit 1)
|
||||
(body_style 1)
|
||||
(exclude_from_sim no)
|
||||
(in_bom yes)
|
||||
(on_board yes)
|
||||
(in_pos_files yes)
|
||||
(dnp no)
|
||||
(uuid "5526d125-8107-4dba-85ca-4b5826ea8f92")
|
||||
(property "Reference" "#PWR0tvs01"
|
||||
(at 41.91 105.41 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
(property "Value" "GND"
|
||||
(at 38.862 105.41 0)
|
||||
(show_name no)
|
||||
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|
||||
(effects
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||||
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||||
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||||
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||||
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|
||||
(property "Footprint" ""
|
||||
(at 38.1 105.41 0)
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||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
(property "Datasheet" ""
|
||||
(at 38.1 105.41 0)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
(effects
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||||
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||||
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|
||||
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|
||||
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|
||||
)
|
||||
(property "Description" "Power symbol creates a global label with name \"GND\" , ground"
|
||||
(at 38.1 105.41 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
(effects
|
||||
(font
|
||||
(size 1.27 1.27)
|
||||
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|
||||
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|
||||
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|
||||
(pin "1"
|
||||
(uuid "5f620c5e-fe2f-4449-8fb6-9983f0d25b83")
|
||||
)
|
||||
(instances
|
||||
(project "re-bba-rb"
|
||||
(path "/dbb182a6-d579-468e-b98b-6f0950da9e3a/1b071f68-b4ea-469c-942f-de06380c9077"
|
||||
(reference "#PWR0tvs01")
|
||||
(unit 1)
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
(symbol
|
||||
(lib_id "Device:R")
|
||||
(at 68.58 96.52 90)
|
||||
@@ -2196,6 +2991,118 @@
|
||||
)
|
||||
)
|
||||
)
|
||||
(symbol
|
||||
(lib_id "Device:D_Zener")
|
||||
(at 50.8 86.36 0)
|
||||
(unit 1)
|
||||
(body_style 1)
|
||||
(exclude_from_sim no)
|
||||
(in_bom yes)
|
||||
(on_board yes)
|
||||
(in_pos_files yes)
|
||||
(dnp no)
|
||||
(uuid "f1ace983-18bf-4781-be5e-b6b0e761dbc3")
|
||||
(property "Reference" "D3"
|
||||
(at 50.8 82.55 0)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
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|
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|
||||
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|
||||
(property "Value" "SMAJ12A"
|
||||
(at 50.8 90.17 0)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
(effects
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(font
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||||
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|
||||
)
|
||||
)
|
||||
(property "Footprint" "Diode_SMD:D_SMA"
|
||||
(at 50.8 86.36 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
(effects
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||||
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|
||||
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|
||||
(property "Datasheet" ""
|
||||
(at 50.8 86.36 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
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|
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|
||||
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|
||||
)
|
||||
)
|
||||
(property "Description" "12V unidirectional TVS, 400W (10/1000us), clamps 12V_EXI (SP1 pin 5) against surge/ESD; K (cathode) to rail, A (anode) to GND"
|
||||
(at 50.8 86.36 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
(effects
|
||||
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|
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||||
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|
||||
)
|
||||
)
|
||||
(property "MPN" "SMAJ12A"
|
||||
(at 50.8 86.36 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
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||||
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|
||||
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|
||||
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|
||||
)
|
||||
)
|
||||
(property "Manufacturer" "Hongjiacheng"
|
||||
(at 50.8 86.36 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
(effects
|
||||
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|
||||
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|
||||
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|
||||
)
|
||||
)
|
||||
(property "LCSC" "C19077531"
|
||||
(at 50.8 86.36 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
(effects
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
)
|
||||
(pin "1"
|
||||
(uuid "404c7c3b-7b98-42aa-8ee1-76fcfd52af7f")
|
||||
)
|
||||
(pin "2"
|
||||
(uuid "c5f4fa95-898e-4809-857f-89db0f25c0d7")
|
||||
)
|
||||
(instances
|
||||
(project "re-bba-rb"
|
||||
(path "/dbb182a6-d579-468e-b98b-6f0950da9e3a/1b071f68-b4ea-469c-942f-de06380c9077"
|
||||
(reference "D3")
|
||||
(unit 1)
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
(symbol
|
||||
(lib_id "power:GND")
|
||||
(at 74.93 78.74 90)
|
||||
|
||||
@@ -1,5 +1,6 @@
|
||||
(fp_lib_table
|
||||
(version 7)
|
||||
(lib (name "gc") (type "KiCad") (uri "${KIPRJMOD}/gc.pretty") (options "") (descr ""))
|
||||
(lib (name "hardware") (type "KiCad") (uri "${KIPRJMOD}/..") (options "") (descr ""))
|
||||
(lib (name "sp1_test_plug") (type "KiCad") (uri "${KIPRJMOD}/../sp1_test_plug") (options "") (descr ""))
|
||||
)
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -24,3 +24,131 @@
|
||||
(severity warning)
|
||||
(condition "A.NetClass == 'PowerLV'")
|
||||
(constraint track_width (min 0.25mm)))
|
||||
|
||||
# ---------------------------------------------------------------------------
|
||||
# JLCPCB manufacturing capability floor (standard multi-layer tier), pulled
|
||||
# from jlcpcb.com/capabilities/pcb-capabilities. These are "the board cannot
|
||||
# physically be made this way" limits, not house-style margins - severity is
|
||||
# "error" because violating one means a rejected/reworked fab order, not just
|
||||
# a style nit. They sit BELOW the netclass defaults above (0.2-0.3mm), so on
|
||||
# a board routed to house style they should never fire; they exist as a
|
||||
# backstop for hand-tweaked geometry (e.g. necking into a fine-pitch pin)
|
||||
# that dips below what JLCPCB can actually etch/drill.
|
||||
#
|
||||
# NOT covered here (no DRC constraint type exists for these - check manually
|
||||
# before ordering):
|
||||
# - Board thickness: JLCPCB stocks 0.6/0.8/1.0/1.2/1.6/2.0mm. This board's
|
||||
# stackup sums to 1.1412mm, which is NOT one of those - confirm with
|
||||
# JLCPCB's stackup tool (their impedance-controlled 4-layer config can
|
||||
# produce non-stock totals like this deliberately) before ordering.
|
||||
# - Solder mask minimum bridge/dam width (0.10mm standard, 0.13mm black/
|
||||
# white): no matching KiCad custom-rule constraint type as of this
|
||||
# version.
|
||||
# - NPTH minimum hole size (0.50mm): skipped - no confirmed condition
|
||||
# syntax to select NPTH-only pads without risking a rule that silently
|
||||
# never matches; the general hole_size floor below still catches any
|
||||
# NPTH hole below the PTH/via floor, just not the tighter 0.50mm NPTH-
|
||||
# specific one.
|
||||
|
||||
(rule "JLCPCB min copper trace width (0.09mm)"
|
||||
(severity error)
|
||||
(constraint track_width (min 0.09mm)))
|
||||
|
||||
(rule "JLCPCB min copper clearance (0.09mm)"
|
||||
(severity error)
|
||||
(constraint clearance (min 0.09mm)))
|
||||
|
||||
(rule "JLCPCB min via/PTH drill (0.15mm)"
|
||||
(severity error)
|
||||
(constraint hole_size (min 0.15mm)))
|
||||
|
||||
(rule "JLCPCB min via pad diameter (0.25mm)"
|
||||
(severity error)
|
||||
(constraint via_diameter (min 0.25mm)))
|
||||
|
||||
(rule "JLCPCB min hole-to-hole spacing (0.2mm)"
|
||||
(severity error)
|
||||
(constraint hole_to_hole (min 0.2mm)))
|
||||
|
||||
(rule "JLCPCB min hole-to-copper clearance (0.2mm)"
|
||||
(severity error)
|
||||
(constraint hole_clearance (min 0.2mm)))
|
||||
|
||||
(rule "JLCPCB min silkscreen line/text thickness (0.15mm, front)"
|
||||
(severity warning)
|
||||
(layer "F.SilkS")
|
||||
(constraint text_thickness (min 0.15mm)))
|
||||
|
||||
(rule "JLCPCB min silkscreen line/text thickness (0.15mm, back)"
|
||||
(severity warning)
|
||||
(layer "B.SilkS")
|
||||
(constraint text_thickness (min 0.15mm)))
|
||||
|
||||
(rule "JLCPCB min silkscreen text height (1.0mm, front)"
|
||||
(severity warning)
|
||||
(layer "F.SilkS")
|
||||
(constraint text_height (min 1.0mm)))
|
||||
|
||||
(rule "JLCPCB min silkscreen text height (1.0mm, back)"
|
||||
(severity warning)
|
||||
(layer "B.SilkS")
|
||||
(constraint text_height (min 1.0mm)))
|
||||
|
||||
(rule "JLCPCB min silkscreen-to-pad clearance (0.15mm, front)"
|
||||
(severity warning)
|
||||
(layer "F.SilkS")
|
||||
(constraint silk_clearance (min 0.15mm)))
|
||||
|
||||
(rule "JLCPCB min silkscreen-to-pad clearance (0.15mm, back)"
|
||||
(severity warning)
|
||||
(layer "B.SilkS")
|
||||
(constraint silk_clearance (min 0.15mm)))
|
||||
|
||||
# ---------------------------------------------------------------------------
|
||||
# Differential pair geometry vs calculated target impedance. The USB_DP/ETH_DP
|
||||
# netclasses (0.25/0.15mm, 0.2/0.14mm) only set the DEFAULT for new routing -
|
||||
# same caveat as the power-rail rules above, KiCad does not enforce a
|
||||
# netclass's width/gap on already-routed copper. These rules close that gap:
|
||||
# they check the geometry actually laid down, not just what a fresh route
|
||||
# would use, so re-routing to the wrong default (the original bug that had
|
||||
# USB sitting at ~113ohm on the Default netclass's 0.2/0.25mm) gets caught by
|
||||
# DRC instead of requiring another hand calculation to notice.
|
||||
#
|
||||
# Target values and their impedance were derived by hand (IPC-2141-style
|
||||
# edge-coupled microstrip formula) from this board's actual stackup - F.Cu/
|
||||
# B.Cu are symmetric microstrip over In1.Cu/In2.Cu respectively (both 0.2104mm
|
||||
# FR4 dielectrics, same εr), so one target pair covers a net whether it's
|
||||
# routed on F.Cu or briefly detours to B.Cu for a crossover. Severity is
|
||||
# "error": these two nets only exist to hit a controlled-impedance target, so
|
||||
# missing it isn't a style nit like the power-rail/silkscreen rules above -
|
||||
# it's the one thing the routing was actually for.
|
||||
# USB_DP: 0.25mm width / 0.15mm gap -> ~91ohm (target 90ohm +/-15%)
|
||||
# ETH_DP: 0.20mm width / 0.14mm gap -> ~100ohm (target 100ohm +/-15%)
|
||||
# track_width keeps a +/-0.02mm max band (routing precision). diff_pair_gap
|
||||
# has NO max: a max bound sounds right but false-flags normal pad fanout,
|
||||
# where P/N necessarily diverge for a few mm right at the pad before
|
||||
# converging into the coupled run - DRC can't tell that apart from a
|
||||
# genuinely uncoupled long run, and real routing hit gaps of 0.65-1.65mm on
|
||||
# fanout stubs vs a ~0.16mm max here. min still catches the case that matters
|
||||
# (traces routed too close, i.e. below the fab clearance floor); max on gap
|
||||
# only matters over a long uncoupled run, which is a length-matching/loss
|
||||
# question, not something this board-wide rule can safely judge per-segment.
|
||||
#
|
||||
# Covers both halves of the D1/D4/D5 split-net TVS pattern: USB_DP now
|
||||
# matches FT_DP/FT_DN (D1's chip-side pins) alongside USB_D+/USB_D-, and
|
||||
# ETH_DP matches PHY_TX_P/PHY_TX_N/PHY_RX_P/PHY_RX_N (D4/D5's chip-side pins)
|
||||
# alongside ETH_TX_P/N and ETH_RX_P/N - see netclass_patterns in
|
||||
# re-bba-rb.kicad_pro. Without that, the chip-side half of each pair falls
|
||||
# back to Default and silently skips the impedance target.
|
||||
|
||||
(rule "USB differential pair width/gap (target ~90ohm)"
|
||||
(severity error)
|
||||
(condition "A.NetClass == 'USB_DP'")
|
||||
(constraint track_width (min 0.23mm) (opt 0.25mm) (max 0.27mm))
|
||||
(constraint diff_pair_gap (min 0.13mm) (opt 0.15mm)))
|
||||
|
||||
(rule "Ethernet differential pair width/gap (target ~100ohm)"
|
||||
(severity error)
|
||||
(condition "A.NetClass == 'ETH_DP'")
|
||||
(constraint track_width (min 0.18mm) (opt 0.20mm) (max 0.22mm))
|
||||
(constraint diff_pair_gap (min 0.12mm) (opt 0.14mm)))
|
||||
|
||||
+6829
-5216
File diff suppressed because it is too large
Load Diff
@@ -1,6 +1,6 @@
|
||||
{
|
||||
"board": {
|
||||
"active_layer": 0,
|
||||
"active_layer": 1,
|
||||
"active_layer_preset": "",
|
||||
"auto_track_width": true,
|
||||
"hidden_netclasses": [],
|
||||
@@ -53,7 +53,7 @@
|
||||
"board_outline_area",
|
||||
"ly_points"
|
||||
],
|
||||
"visible_layers": "ffffffff_ffffffff_ffffffff_ffffffaf",
|
||||
"visible_layers": "ffffffff_ffffffff_ffffffff_ffffffff",
|
||||
"zone_display_mode": 0
|
||||
},
|
||||
"git": {
|
||||
|
||||
@@ -525,6 +525,24 @@
|
||||
"via_drill": 0.3,
|
||||
"wire_width": 6
|
||||
},
|
||||
{
|
||||
"bus_width": 12,
|
||||
"clearance": 0.15,
|
||||
"diff_pair_gap": 0.14,
|
||||
"diff_pair_width": 0.2,
|
||||
"line_style": 0,
|
||||
"microvia_diameter": 0.3,
|
||||
"microvia_drill": 0.1,
|
||||
"name": "ETH_DP",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"priority": 3,
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.2,
|
||||
"tuning_profile": "",
|
||||
"via_diameter": 0.6,
|
||||
"via_drill": 0.3,
|
||||
"wire_width": 6
|
||||
},
|
||||
{
|
||||
"bus_width": 12,
|
||||
"clearance": 0.15,
|
||||
@@ -560,6 +578,24 @@
|
||||
"via_diameter": 0.6,
|
||||
"via_drill": 0.3,
|
||||
"wire_width": 6
|
||||
},
|
||||
{
|
||||
"bus_width": 12,
|
||||
"clearance": 0.15,
|
||||
"diff_pair_gap": 0.15,
|
||||
"diff_pair_width": 0.25,
|
||||
"line_style": 0,
|
||||
"microvia_diameter": 0.3,
|
||||
"microvia_drill": 0.1,
|
||||
"name": "USB_DP",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"priority": 2,
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.25,
|
||||
"tuning_profile": "",
|
||||
"via_diameter": 0.6,
|
||||
"via_drill": 0.3,
|
||||
"wire_width": 6
|
||||
}
|
||||
],
|
||||
"meta": {
|
||||
@@ -603,6 +639,54 @@
|
||||
{
|
||||
"netclass": "PowerLV",
|
||||
"pattern": "*VDD1_ISO*"
|
||||
},
|
||||
{
|
||||
"netclass": "USB_DP",
|
||||
"pattern": "*USB_D+*"
|
||||
},
|
||||
{
|
||||
"netclass": "USB_DP",
|
||||
"pattern": "*USB_D-*"
|
||||
},
|
||||
{
|
||||
"netclass": "ETH_DP",
|
||||
"pattern": "*ETH_TX_P*"
|
||||
},
|
||||
{
|
||||
"netclass": "ETH_DP",
|
||||
"pattern": "*ETH_TX_N*"
|
||||
},
|
||||
{
|
||||
"netclass": "ETH_DP",
|
||||
"pattern": "*ETH_RX_P*"
|
||||
},
|
||||
{
|
||||
"netclass": "ETH_DP",
|
||||
"pattern": "*ETH_RX_N*"
|
||||
},
|
||||
{
|
||||
"netclass": "ETH_DP",
|
||||
"pattern": "*PHY_TX_P*"
|
||||
},
|
||||
{
|
||||
"netclass": "ETH_DP",
|
||||
"pattern": "*PHY_TX_N*"
|
||||
},
|
||||
{
|
||||
"netclass": "ETH_DP",
|
||||
"pattern": "*PHY_RX_P*"
|
||||
},
|
||||
{
|
||||
"netclass": "ETH_DP",
|
||||
"pattern": "*PHY_RX_N*"
|
||||
},
|
||||
{
|
||||
"netclass": "USB_DP",
|
||||
"pattern": "*FT_DP*"
|
||||
},
|
||||
{
|
||||
"netclass": "USB_DP",
|
||||
"pattern": "*FT_DN*"
|
||||
}
|
||||
]
|
||||
},
|
||||
@@ -872,7 +956,7 @@
|
||||
"uuid": "dbb182a6-d579-468e-b98b-6f0950da9e3a"
|
||||
}
|
||||
],
|
||||
"used_designators": "C17,#PWR090e1-3,#PWR44-50,R20-21",
|
||||
"used_designators": "R20-21,#PWR44-50,#PWR090e1-3,C17",
|
||||
"variants": []
|
||||
},
|
||||
"sheets": [
|
||||
|
||||
@@ -3,4 +3,5 @@
|
||||
(lib (name "GameCube")(type "KiCad")(uri "${KIPRJMOD}/../sp1_test_plug/symbols/GameCube.kicad_sym")(options "")(descr "GameCube SP1 connector"))
|
||||
(lib (name "TPS562201DDCR")(type "KiCad")(uri "${KIPRJMOD}/../TPS562201DDCR.kicad_sym")(options "")(descr "TPS562201 buck (custom)"))
|
||||
(lib (name "HR911105A")(type "KiCad")(uri "${KIPRJMOD}/../HR911105A.kicad_sym")(options "")(descr "HanRun HR911105A RJ45 magjack (custom)"))
|
||||
(lib (name "PUSB3AB6Z_ES")(type "KiCad")(uri "${KIPRJMOD}/../PUSB3AB6Z_ES.kicad_sym")(options "")(descr "Nexperia PUSB3AB6Z 6-ch 3.3V 0.15pF TVS array (ElecSuper 2nd source)"))
|
||||
)
|
||||
|
||||
Reference in New Issue
Block a user