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Finished the PCB design

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This commit is contained in:
Dennis Brentjes
2026-07-17 21:35:02 +02:00
parent db457a02c3
commit 3547302ec2
22 changed files with 12299 additions and 5279 deletions
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hardware/re-bba-rb/re-bba-rb.kicad_pro
+85 -1
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@@ -525,6 +525,24 @@
"via_drill": 0.3,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.15,
"diff_pair_gap": 0.14,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "ETH_DP",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 3,
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.2,
"tuning_profile": "",
"via_diameter": 0.6,
"via_drill": 0.3,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.15,
@@ -560,6 +578,24 @@
"via_diameter": 0.6,
"via_drill": 0.3,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.15,
"diff_pair_gap": 0.15,
"diff_pair_width": 0.25,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "USB_DP",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 2,
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.25,
"tuning_profile": "",
"via_diameter": 0.6,
"via_drill": 0.3,
"wire_width": 6
}
],
"meta": {
@@ -603,6 +639,54 @@
{
"netclass": "PowerLV",
"pattern": "*VDD1_ISO*"
},
{
"netclass": "USB_DP",
"pattern": "*USB_D+*"
},
{
"netclass": "USB_DP",
"pattern": "*USB_D-*"
},
{
"netclass": "ETH_DP",
"pattern": "*ETH_TX_P*"
},
{
"netclass": "ETH_DP",
"pattern": "*ETH_TX_N*"
},
{
"netclass": "ETH_DP",
"pattern": "*ETH_RX_P*"
},
{
"netclass": "ETH_DP",
"pattern": "*ETH_RX_N*"
},
{
"netclass": "ETH_DP",
"pattern": "*PHY_TX_P*"
},
{
"netclass": "ETH_DP",
"pattern": "*PHY_TX_N*"
},
{
"netclass": "ETH_DP",
"pattern": "*PHY_RX_P*"
},
{
"netclass": "ETH_DP",
"pattern": "*PHY_RX_N*"
},
{
"netclass": "USB_DP",
"pattern": "*FT_DP*"
},
{
"netclass": "USB_DP",
"pattern": "*FT_DN*"
}
]
},
@@ -872,7 +956,7 @@
"uuid": "dbb182a6-d579-468e-b98b-6f0950da9e3a"
}
],
"used_designators": "C17,#PWR090e1-3,#PWR44-50,R20-21",
"used_designators": "R20-21,#PWR44-50,#PWR090e1-3,C17",
"variants": []
},
"sheets": [