Fixes the power traces.

2026-07-09 20:08:05 +02:00
parent 620ae5cd64
commit 5727fc74a3
6 changed files with 6960 additions and 5615 deletions
@@ -524,6 +524,42 @@
        "via_diameter": 0.6,
        "via_drill": 0.3,
        "wire_width": 6
+      },
+      {
+        "bus_width": 12,
+        "clearance": 0.15,
+        "diff_pair_gap": 0.25,
+        "diff_pair_width": 0.2,
+        "line_style": 0,
+        "microvia_diameter": 0.3,
+        "microvia_drill": 0.1,
+        "name": "Power",
+        "pcb_color": "rgba(0, 0, 0, 0.000)",
+        "priority": 0,
+        "schematic_color": "rgba(0, 0, 0, 0.000)",
+        "track_width": 0.3,
+        "tuning_profile": "",
+        "via_diameter": 0.6,
+        "via_drill": 0.3,
+        "wire_width": 6
+      },
+      {
+        "bus_width": 12,
+        "clearance": 0.15,
+        "diff_pair_gap": 0.25,
+        "diff_pair_width": 0.2,
+        "line_style": 0,
+        "microvia_diameter": 0.3,
+        "microvia_drill": 0.1,
+        "name": "PowerLV",
+        "pcb_color": "rgba(0, 0, 0, 0.000)",
+        "priority": 1,
+        "schematic_color": "rgba(0, 0, 0, 0.000)",
+        "track_width": 0.25,
+        "tuning_profile": "",
+        "via_diameter": 0.6,
+        "via_drill": 0.3,
+        "wire_width": 6
      }
    ],
    "meta": {
@@ -531,7 +567,44 @@
    },
    "net_colors": null,
    "netclass_assignments": null,
-    "netclass_patterns": []
+    "netclass_patterns": [
+      {
+        "netclass": "Power",
+        "pattern": "*3V3*"
+      },
+      {
+        "netclass": "Power",
+        "pattern": "*12V*"
+      },
+      {
+        "netclass": "Power",
+        "pattern": "*SWN*"
+      },
+      {
+        "netclass": "Power",
+        "pattern": "*VBUS*"
+      },
+      {
+        "netclass": "PowerLV",
+        "pattern": "*1V2*"
+      },
+      {
+        "netclass": "PowerLV",
+        "pattern": "*VCORE*"
+      },
+      {
+        "netclass": "PowerLV",
+        "pattern": "*VCCPLL*"
+      },
+      {
+        "netclass": "PowerLV",
+        "pattern": "*VPLL*"
+      },
+      {
+        "netclass": "PowerLV",
+        "pattern": "*VDD1_ISO*"
+      }
+    ]
  },
  "pcbnew": {
    "last_paths": {
@@ -799,7 +872,7 @@
        "uuid": "dbb182a6-d579-468e-b98b-6f0950da9e3a"
      }
    ],
-    "used_designators": "",
+    "used_designators": "R20-21",
    "variants": []
  },
  "sheets": [