Finished the board including the connector and mousebites

2026-07-22 22:02:12 +02:00
parent a86aa255f1
commit 5828d6a388
16 changed files with 11159 additions and 6453 deletions
@@ -60,7 +60,9 @@ class BBATop(Elaboratable):
        # iCEbreaker — see synth.py).  panel_led bit order matches StatusPanel.
        self._status_panel = status_panel
        # Optional UART debug console (8N1 115200, sync domain).
-        # uart_tx → FT2232H Channel B pin 9; uart_rx ← pin 6.
+        # uart_tx → FT2232H Channel B (net UART_RXD, pin 19);
+        # uart_rx ← FT2232H Channel B (net UART_TXD, pin 18) — net names are
+        # FTDI-perspective, so this is not a naming mismatch, see synth.py.
        self._uart_console = uart_console

        # EXI (GC side)