Finished the board including the connector and mousebites
This commit is contained in:
Dennis Brentjes
@@ -0,0 +1,231 @@
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(footprint "SP1_eth2sp1_reference"
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(version 20260206)
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||||
(generator "pcbnew")
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||||
(generator_version "10.0")
|
||||
(layer "F.Cu")
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||||
(descr "SP1 gold-finger contact geometry from the eth2sp1 open-source project (github.com/jochemvdmeulen/eth2sp1) for visual/DRC reference comparison against this board's own J3. Pad length: eth2sp1's original 7mm, extended to 13.5mm + board thickness (1.1412mm) = 14.6412mm, then trimmed 1.0mm to 13.6412mm - anchored at the board-edge-proximal pad edge (0.6mm inboard of the nose, matching eth2sp1's original tip clearance) with all length changes taken from the far/inner edge. REFERENCE ONLY - not this board's actual connector (J3 uses hand-solder-insert thru-hole pads, not bare gold fingers). Always DNP. The small nose/edge outline is on Cmts.User (reference only, NOT Edge.Cuts) since a second disconnected Edge.Cuts fragment breaks the board's outline closure check.")
|
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(tags "SP1 GameCube reference eth2sp1 DNP")
|
||||
(property "Reference" "REF**"
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||||
(at 0 2 0)
|
||||
(unlocked yes)
|
||||
(layer "F.SilkS")
|
||||
(uuid "340c217a-0562-4247-ace1-d31c792bb209")
|
||||
(effects
|
||||
(font
|
||||
(size 1 1)
|
||||
(thickness 0.15)
|
||||
)
|
||||
)
|
||||
)
|
||||
(property "Value" "SP1_eth2sp1_reference"
|
||||
(at 0 4 0)
|
||||
(unlocked yes)
|
||||
(layer "F.Fab")
|
||||
(uuid "8b032738-6eb1-429c-af4f-ba212781503c")
|
||||
(effects
|
||||
(font
|
||||
(size 1 1)
|
||||
(thickness 0.15)
|
||||
)
|
||||
)
|
||||
)
|
||||
(property "Footprint" "hardware:SP1_eth2sp1_reference"
|
||||
(at 0 5 0)
|
||||
(unlocked yes)
|
||||
(layer "F.Fab")
|
||||
(hide yes)
|
||||
(uuid "25053893-94be-416c-9ba4-cce6dec782d2")
|
||||
(effects
|
||||
(font
|
||||
(size 1 1)
|
||||
(thickness 0.15)
|
||||
)
|
||||
)
|
||||
)
|
||||
(property "Datasheet" ""
|
||||
(at 0 5 0)
|
||||
(unlocked yes)
|
||||
(layer "F.Fab")
|
||||
(hide yes)
|
||||
(uuid "87da103c-056f-4b3b-b875-aed40f5a5ce5")
|
||||
(effects
|
||||
(font
|
||||
(size 1 1)
|
||||
(thickness 0.15)
|
||||
)
|
||||
)
|
||||
)
|
||||
(property "Description" ""
|
||||
(at 0 5 0)
|
||||
(unlocked yes)
|
||||
(layer "F.Fab")
|
||||
(hide yes)
|
||||
(uuid "f751e2dc-bf5b-41e2-a5bf-97f5433e2ed0")
|
||||
(effects
|
||||
(font
|
||||
(size 1 1)
|
||||
(thickness 0.15)
|
||||
)
|
||||
)
|
||||
)
|
||||
(fp_line
|
||||
(start 6.5 -6.4)
|
||||
(end 6.5 0)
|
||||
(stroke
|
||||
(width 0.1)
|
||||
(type solid)
|
||||
)
|
||||
(layer "Cmts.User")
|
||||
(uuid "a26abfe7-0d15-4f9d-86b0-59f940f6ed12")
|
||||
)
|
||||
(fp_line
|
||||
(start 5.9 -7)
|
||||
(end -5.9 -7)
|
||||
(stroke
|
||||
(width 0.1)
|
||||
(type solid)
|
||||
)
|
||||
(layer "Cmts.User")
|
||||
(uuid "fa1cc527-0999-43e3-bbee-4911cef99d9d")
|
||||
)
|
||||
(fp_line
|
||||
(start -6.5 -6.4)
|
||||
(end -6.5 0)
|
||||
(stroke
|
||||
(width 0.1)
|
||||
(type solid)
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||||
)
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||||
(layer "Cmts.User")
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||||
(uuid "dfa6c775-2697-4bc0-98b5-4153a6dce288")
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||||
)
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||||
(fp_arc
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||||
(start 5.9 -7)
|
||||
(mid 6.324264 -6.824264)
|
||||
(end 6.5 -6.4)
|
||||
(stroke
|
||||
(width 0.1)
|
||||
(type solid)
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||||
)
|
||||
(layer "Cmts.User")
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||||
(uuid "eba98ff8-ca8d-4f65-b41f-361504a39c10")
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||||
)
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||||
(fp_arc
|
||||
(start -6.5 -6.4)
|
||||
(mid -6.324264 -6.824264)
|
||||
(end -5.9 -7)
|
||||
(stroke
|
||||
(width 0.1)
|
||||
(type solid)
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||||
)
|
||||
(layer "Cmts.User")
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||||
(uuid "50917725-a0b9-4d21-8808-9d0fb16672aa")
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||||
)
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(fp_text user "${REFERENCE}"
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||||
(at 0 2.5 0)
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||||
(unlocked yes)
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||||
(layer "F.Fab")
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||||
(uuid "5cedd119-6420-42e7-a09a-2282fd0981a7")
|
||||
(effects
|
||||
(font
|
||||
(size 1 1)
|
||||
(thickness 0.15)
|
||||
)
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||||
)
|
||||
)
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||||
(pad "1" smd rect
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(at -5.5 0.4206 180)
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(size 1.5 13.6412)
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(layers "B.Cu" "B.Mask")
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(pinfunction "EXTIN")
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(pintype "input+no_connect")
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(uuid "8160b939-ce92-4631-9852-2a26e1aea0cc")
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)
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(pad "2" smd rect
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||||
(at -4.5 0.4206 180)
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(size 1.5 13.6412)
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(layers "F.Cu" "F.Mask")
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(pinfunction "GNDs")
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(pintype "input")
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(uuid "4dc936d5-4eb4-4ff3-9e33-5d98412966b1")
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||||
)
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||||
(pad "3" smd rect
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(at -3.5 0.4206 180)
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(size 1.5 13.6412)
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(layers "B.Cu" "B.Mask")
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(pinfunction "INT")
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(pintype "input")
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(uuid "4ed42ce0-553a-4c9f-b206-078ea82c1d06")
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)
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(pad "4" smd rect
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(at -2.5 0.4206 180)
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(size 1.5 13.6412)
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(layers "F.Cu" "F.Mask")
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(pinfunction "CLK")
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(pintype "input")
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(uuid "dbfb64b2-7d83-416d-9b70-f19bd0546f5b")
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)
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(pad "5" smd rect
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||||
(at -1.5 0.4206 180)
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(size 1.5 13.6412)
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(layers "B.Cu" "B.Mask")
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(pinfunction "12V")
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(pintype "input+no_connect")
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(uuid "64558319-3b87-44be-8057-e75cad34cf21")
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||||
)
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||||
(pad "6" smd rect
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||||
(at -0.5 0.4206 180)
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(size 1.5 13.6412)
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||||
(layers "F.Cu" "F.Mask")
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||||
(pinfunction "DO")
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||||
(pintype "input")
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||||
(uuid "716d87a9-4752-4c43-8aeb-01f3c13f2e85")
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||||
)
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||||
(pad "7" smd rect
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||||
(at 0.5 0.4206 180)
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||||
(size 1.5 13.6412)
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||||
(layers "B.Cu" "B.Mask")
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||||
(pinfunction "3V3")
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||||
(pintype "input")
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||||
(uuid "5cb34674-b690-4198-b249-3c15fd2bb685")
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||||
)
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||||
(pad "8" smd rect
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||||
(at 1.5 0.4206 180)
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||||
(size 1.5 13.6412)
|
||||
(layers "F.Cu" "F.Mask")
|
||||
(pinfunction "3V3")
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||||
(pintype "input")
|
||||
(uuid "85c91145-35ba-489c-adcb-e7b52fdec5a5")
|
||||
)
|
||||
(pad "9" smd rect
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||||
(at 2.5 0.4206 180)
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||||
(size 1.5 13.6412)
|
||||
(layers "B.Cu" "B.Mask")
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||||
(pinfunction "DI")
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||||
(pintype "input")
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||||
(uuid "1777659c-c4af-4ff2-ba96-b22c04ae7ed4")
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||||
)
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||||
(pad "10" smd rect
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||||
(at 3.5 0.4206 180)
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||||
(size 1.5 13.6412)
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||||
(layers "F.Cu" "F.Mask")
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||||
(pinfunction "CS")
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(pintype "input")
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||||
(uuid "92543d61-f50b-414e-8279-9d0f04454364")
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||||
)
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||||
(pad "11" smd rect
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||||
(at 4.5 0.4206 180)
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||||
(size 1.5 13.6412)
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||||
(layers "B.Cu" "B.Mask")
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||||
(pinfunction "GND")
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||||
(pintype "input")
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||||
(uuid "bb75cdf0-85ed-448f-81fe-d8aee586b841")
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||||
)
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||||
(pad "12" smd rect
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||||
(at 5.5 0.4206 180)
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||||
(size 1.5 13.6412)
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||||
(layers "F.Cu" "F.Mask")
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||||
(pinfunction "GND")
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||||
(pintype "input")
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||||
(uuid "9eb6e23f-9a0f-4150-aafe-e36de21406d2")
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)
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)
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@@ -0,0 +1,121 @@
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# CPL rotation corrections — re-bba-rb
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`re-bba-rb-cpl.csv` is generated from `kicad-cli pcb export pos` (raw KiCad
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rotation values), **then hand-corrected** for the parts below before each
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regeneration. This file exists because that correction step is easy to lose
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silently — regenerating the CPL "the normal way" wipes it out, and there is
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no automated check that would catch that. Read this before touching the CPL.
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## Why this exists
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KiCad's per-footprint rotation is measured from an arbitrary reference baked
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into whoever drew that footprint — it does not reliably match what JLCPCB's
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placement machine expects. This is a well-known, generic problem (see
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`cpl_rotations_db.csv` from the JLCKicadTools / kicad-jlcpcb-tools projects
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for the community's attempt at a fix), but **the generic community
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correction table was tried on this board and found wrong** — it claims
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`LQFP-: 270°`, but on this exact board/toolchain pairing (KiCad 10 +
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`kicad-cli pcb export pos`, not the dedicated plugin) the raw LQFP/QFN
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rotation is already correct. The generic table's values are calibrated
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against that plugin's own raw-rotation baseline, which is not the same
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baseline `kicad-cli`'s raw CSV export produces (different Y-axis handling
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between the two tools). **Do not reapply the community table wholesale to
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this board.** Every correction below was derived per-part from direct visual
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verification against JLCPCB's placement-preview render, not from that table.
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## Rotation sign convention
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The CPL uses JLCPCB's Y-up coordinate frame (`kicad-cli`'s csv pos format
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already negates Y from KiCad's native Y-down). In that frame, **increasing
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rotation angle is counter-clockwise** (standard math convention). So when
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the user reports "needs N degrees clockwise", the correction applied is
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**`new = (old - N) % 360`**, not `+N`. Get this backwards and every fix
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lands 2×N off instead of correct.
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## How the correction was (re-)applied each time
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```python
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import csv
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corrections = { 'REF': degrees, ... } # positive = CCW, negative = CW
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with open('re-bba-rb-cpl.csv', newline='') as f:
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rows = list(csv.DictReader(f))
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for r in rows:
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if r['Designator'] in corrections:
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old = float(r['Rotation'])
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new = (old + corrections[r['Designator']]) % 360
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r['Rotation'] = f"{new:.6f}"
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with open('re-bba-rb-cpl.csv', 'w', newline='') as f:
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writer = csv.DictWriter(f, fieldnames=['Designator','Mid X','Mid Y','Layer','Rotation'])
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writer.writeheader()
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writer.writerows(rows)
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```
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When regenerating the CPL from scratch (e.g. after a reroute or component
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move), **re-run `kicad-cli pcb export pos` for fresh positions, then
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reapply every correction below** — don't just diff/copy the old file, since
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positions can legitimately change while rotations still need the same
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correction offset applied on top.
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## Confirmed correct as-is — apply NO correction
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- **U8, U11 (LQFP-48/64)**, **U9 (QFN-48)** — "all large chips are right"
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(user, direct placement-preview check). Raw KiCad rotation is correct.
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- **U4 (SOT-23-5)** — confirmed good *after* the -90° family correction
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below was applied (net rotation 270°, i.e. raw 0° − 90°).
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- **J2 (HR911105A magjack, rot=90° in the PCB file)** — not a CPL-rotation
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question (J2 doesn't need per-part correction below, it's not in the CPL
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correction set), but its physical orientation was independently verified:
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the RJ45 signal pins (pins 1–8, footprint local +Y) map to absolute −X
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under the board's 90° placement rotation, which correctly faces the
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board's tongue/cable-exit edge. Pin 1 appearing to "face outside the
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board" in the placement render is *expected*, not a defect — the RJ45
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contacts are always near the cable-insertion opening by construction.
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## Corrections applied (all currently in `re-bba-rb-cpl.csv`)
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Each row: designator, package, raw→corrected, confidence.
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| Ref | Package | Raw | Corrected | Confidence |
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|---|---|---|---|---|
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| U7 | SOIC-8 | 90° | **180°** | Reconstructed hypothesis (see below) — not independently re-confirmed |
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| U10 | SOIC-8 | 0° | **90°** | Reconstructed hypothesis — not independently re-confirmed |
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||||
| D1 | SOT-23-6 | 0° | **270°** | Reconstructed hypothesis — not independently re-confirmed |
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| D4 | SOT-23-6 | 180° | **90°** | Reconstructed hypothesis — not independently re-confirmed |
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||||
| D5 | SOT-23-6 | 180° | **90°** | Reconstructed hypothesis — not independently re-confirmed |
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||||
| U12 | SOT-23-6 | 180° | **90°** | Reconstructed hypothesis — not independently re-confirmed |
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||||
| U1 | SOT-23-5 | 180° | **0°** (two corrections: -90° then another -90°, user-confirmed both times) | **Confirmed** by direct user feedback, twice |
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| Q1 | SOT-23 (bottom layer) | -90° | **90°** | **Confirmed** ("upside down" = 180°, direction-agnostic) |
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| Q2 | SOT-23 (bottom layer) | -90° | **90°** | **Confirmed** (same as Q1) |
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||||
| D2 | custom `SON50P110X213X50-7` | 0° | **270°** | **Confirmed** ("90° clockwise") |
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||||
| D3 | `Diode_SMD:D_SMA` | 180° | **0°** | **Confirmed** ("180°", direction-agnostic) |
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||||
| C65 | `Capacitor_SMD:CP_Elec_6.3x7.7` | 0° | **180°** | **Confirmed** ("180°", direction-agnostic) |
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||||
| U2 | SOT-583-8 | 180° | **90°** | **Confirmed** ("90° clockwise") |
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||||
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||||
**"Reconstructed hypothesis" parts (U7, U10, D1, D4, D5, U12) explained:**
|
||||
the user reported "SOIC and SOT chips are rotated 90°, direction unsure."
|
||||
Cross-referencing against *earlier* feedback in the same session — where a
|
||||
-90° correction had been applied to the top-layer SOT-23 parts and NOT
|
||||
flagged as wrong, while the same -90° applied to a SOIC part (U10) WAS
|
||||
flagged wrong — implies SOT-23 needs -90° and SOIC needs the opposite,
|
||||
+90°. This is indirect reasoning, not a fresh direct check, and **U1 later
|
||||
proved that even within one confirmed-wrong-by-90°-family, the correction
|
||||
does NOT reliably generalize per package type** (U1 and U4 are both
|
||||
SOT-23-5, both got the -90° family correction, but U1 needed a *second*
|
||||
-90° on top while U4 was already correct) — so treat every "reconstructed
|
||||
hypothesis" row above as **worth a fresh placement-preview check**, not
|
||||
settled fact, despite no contradicting feedback having come in since.
|
||||
|
||||
## Parts never checked at all
|
||||
|
||||
Every 0402/0603/0805 passive (R/C/L), J1/J3/J4 connectors, the custom
|
||||
`U3` footprint (`hardware:SOT95P280X110-6N`), and anything else not listed
|
||||
above is sitting at **raw, unverified KiCad rotation** in the CPL. Passives
|
||||
in symmetric packages are usually fine raw (this matched observed behavior
|
||||
for the ones implicitly checked), but this has not been confirmed
|
||||
part-by-part the way the table above was.
|
||||
|
||||
## Bottom line for whoever picks this up next
|
||||
|
||||
Before ordering assembly, re-check the *entire* board in JLCPCB's (or
|
||||
whatever assembler's) placement preview — this file only covers what's been
|
||||
individually verified so far, not a general guarantee the CPL is correct.
|
||||
+529
-120
File diff suppressed because it is too large
Load Diff
@@ -3433,7 +3433,7 @@
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)
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||||
)
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||||
)
|
||||
(property "MPN" "0402WGF1503TCE"
|
||||
(property "MPN" "RC0402FR-07150KL"
|
||||
(at 0 0 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
@@ -3444,7 +3444,7 @@
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||||
)
|
||||
)
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||||
)
|
||||
(property "Manufacturer" "UNI-ROYAL"
|
||||
(property "Manufacturer" "YAGEO"
|
||||
(at 0 0 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
@@ -3455,7 +3455,7 @@
|
||||
)
|
||||
)
|
||||
)
|
||||
(property "LCSC" "C25755"
|
||||
(property "LCSC" "C93947"
|
||||
(at 0 0 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
@@ -3971,7 +3971,7 @@
|
||||
)
|
||||
)
|
||||
)
|
||||
(property "MPN" "19-217/GHC-YR1S2/3T"
|
||||
(property "MPN" "KT-0603G"
|
||||
(at 33.02 60.96 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
@@ -3982,7 +3982,7 @@
|
||||
)
|
||||
)
|
||||
)
|
||||
(property "LCSC" "C72043"
|
||||
(property "LCSC" "C12624"
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||||
(at 33.02 60.96 0)
|
||||
(hide yes)
|
||||
(show_name no)
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||||
@@ -3993,7 +3993,7 @@
|
||||
)
|
||||
)
|
||||
)
|
||||
(property "Manufacturer" "Everlight"
|
||||
(property "Manufacturer" "Hubei KENTO"
|
||||
(at 33.02 60.96 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
@@ -5244,7 +5244,7 @@
|
||||
)
|
||||
)
|
||||
)
|
||||
(property "MPN" "19-217/GHC-YR1S2/3T"
|
||||
(property "MPN" "KT-0603G"
|
||||
(at 48.26 78.74 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
@@ -5255,7 +5255,7 @@
|
||||
)
|
||||
)
|
||||
)
|
||||
(property "LCSC" "C72043"
|
||||
(property "LCSC" "C12624"
|
||||
(at 48.26 78.74 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
@@ -5266,7 +5266,7 @@
|
||||
)
|
||||
)
|
||||
)
|
||||
(property "Manufacturer" "Everlight"
|
||||
(property "Manufacturer" "Hubei KENTO"
|
||||
(at 48.26 78.74 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
@@ -5758,7 +5758,7 @@
|
||||
(justify left)
|
||||
)
|
||||
)
|
||||
(property "Value" "330"
|
||||
(property "Value" "49.9"
|
||||
(at 36.83 56.07 0)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
@@ -5802,7 +5802,7 @@
|
||||
)
|
||||
)
|
||||
)
|
||||
(property "MPN" "0402WGF3300TCE"
|
||||
(property "MPN" "0402WGF4999TCE"
|
||||
(at 36.83 52.07 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
@@ -5813,7 +5813,7 @@
|
||||
)
|
||||
)
|
||||
)
|
||||
(property "LCSC" "C25104"
|
||||
(property "LCSC" "C25120"
|
||||
(at 36.83 52.07 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
@@ -7123,7 +7123,7 @@
|
||||
(justify left)
|
||||
)
|
||||
)
|
||||
(property "Value" "330"
|
||||
(property "Value" "49.9"
|
||||
(at 52.07 76.39 0)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
@@ -7167,7 +7167,7 @@
|
||||
)
|
||||
)
|
||||
)
|
||||
(property "MPN" "0402WGF3300TCE"
|
||||
(property "MPN" "0402WGF4999TCE"
|
||||
(at 52.07 72.39 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
@@ -7178,7 +7178,7 @@
|
||||
)
|
||||
)
|
||||
)
|
||||
(property "LCSC" "C25104"
|
||||
(property "LCSC" "C25120"
|
||||
(at 52.07 72.39 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
@@ -7358,7 +7358,7 @@
|
||||
)
|
||||
)
|
||||
)
|
||||
(property "MPN" "0402WGF1002TCE"
|
||||
(property "MPN" "RC0402FR-0710KL"
|
||||
(at 0 0 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
@@ -7369,7 +7369,7 @@
|
||||
)
|
||||
)
|
||||
)
|
||||
(property "Manufacturer" "UNI-ROYAL"
|
||||
(property "Manufacturer" "YAGEO"
|
||||
(at 0 0 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
@@ -7380,7 +7380,7 @@
|
||||
)
|
||||
)
|
||||
)
|
||||
(property "LCSC" "C25744"
|
||||
(property "LCSC" "C60490"
|
||||
(at 0 0 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
@@ -7560,7 +7560,7 @@
|
||||
)
|
||||
)
|
||||
)
|
||||
(property "MPN" "0402WGF1002TCE"
|
||||
(property "MPN" "RC0402FR-0710KL"
|
||||
(at 0 0 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
@@ -7571,7 +7571,7 @@
|
||||
)
|
||||
)
|
||||
)
|
||||
(property "Manufacturer" "UNI-ROYAL"
|
||||
(property "Manufacturer" "YAGEO"
|
||||
(at 0 0 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
@@ -7582,7 +7582,7 @@
|
||||
)
|
||||
)
|
||||
)
|
||||
(property "LCSC" "C25744"
|
||||
(property "LCSC" "C60490"
|
||||
(at 0 0 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
|
||||
+207
-37
@@ -6,6 +6,125 @@ manufacturing limits. Status 2026-07-18: **all three critical findings fixed
|
||||
in schematic AND PCB** (ERC 0, DRC 0 errors / 0 unconnected / 0 parity);
|
||||
remaining work is the Functional/Broader/ordering lists below.
|
||||
|
||||
**Status 2026-07-22 (last-check pass):** ERC still clean (2 known-benign
|
||||
`lib_symbol_issues` on the generic Q_NPN_BEC/Q_PNP_BEC library symbols, not
|
||||
real problems). DRC: 0 unconnected items board-wide (incl. J3 — all 24 pads
|
||||
now carry real net copper, confirmed by direct pad/net inspection, not just
|
||||
the ratsnest count); 242 total violations, of which only **4 are errors**
|
||||
(2× `clearance` + 2× `hole_clearance`, two GND vias at (190.78/190.34, 58.58)
|
||||
0 mm from the `/Power/3V3` zone on In2.Cu — see Functional/robustness below),
|
||||
1 `track_dangling` (a 0.06 mm stub on `/exi/EXI_MOSI_RAW` near (188.39,
|
||||
57.52), likely harmless routing debris), and the rest are silkscreen
|
||||
warnings (171 overlap, 60 over-copper, 6 edge-clearance). This session also
|
||||
did extensive photo-based mechanical verification and a real J3 Y-position
|
||||
correction — see "Verify mechanical fit" below — and re-added fiducials with
|
||||
a different footprint/position than this file previously documented.
|
||||
|
||||
**Status 2026-07-24 (major session):** ERC 0 (same 2 known-benign warnings +
|
||||
1 expected `power_pin_not_driven` on J5's `EXI_GND`, see below — not a real
|
||||
problem, that net has no power-symbol driver by design). DRC: 0 unconnected
|
||||
items, 280 total violations — same silkscreen-warning baseline as before
|
||||
plus `npth_inside_courtyard` (27, J5's mouse-bite holes sit close to J2's
|
||||
courtyard, judged benign — holes, not a component body) and 1 harmless
|
||||
`track_dangling`. The 2 GND-vias-vs-3V3-zone short from 2026-07-22 is
|
||||
**gone** (resolved somewhere in this session's PCB work, confirmed via fresh
|
||||
DRC). Gerbers/BOM/CPL all regenerated and verified current as of this pass.
|
||||
Major work this session:
|
||||
- **D6/D8/D9/D12 green LEDs swapped** Everlight 19-217/GHC-YR1S2/3T (C72043,
|
||||
out of stock) → Hubei KENTO KT-0603G (C12624) — same 0603 footprint, same
|
||||
manufacturer family as the already-used red KT-0603R (D7/D11). Series
|
||||
resistors R37/R41/R42 changed 330 Ω → **49.9 Ω** (reused C25120, the same
|
||||
part already on R26–R29 — no new BOM line) to compensate for KT-0603G's
|
||||
higher Vf (3.1 V typ.) and restore comparable brightness (~4 mA vs the
|
||||
~0.6 mA the old resistor value would have given it). D12/D13 (RGB channels,
|
||||
driven directly by the FPGA's `SB_RGBA_DRV` hard macro, no series resistor)
|
||||
need no resistor change — flagged as slightly reduced current-source
|
||||
headroom at the higher Vf, not fixed (nothing to fix, no resistor exists).
|
||||
- [ ] **D13 (yellow, Everlight C72038) and the 10 kΩ 0402 resistor
|
||||
(UNI-ROYAL C25744, used by 12 designators) are ALSO reported out of
|
||||
stock** — real in-stock alternatives were being researched
|
||||
(candidates: Hubei KENTO KT-0603Y/KT-0805Y for D13; YAGEO
|
||||
RC0402FR-0710KL C60490 or Vishay CRCW040210K0FKED C71617 for the
|
||||
10k) but never confirmed/committed — stock claims from web search
|
||||
proved unreliable earlier this session (contradicted by direct
|
||||
JLCPCB part-page checks twice), so these need a live stock check
|
||||
before ordering, same as the green LED did.
|
||||
- **J5 added**: a second SP1 gold-finger connector, footprint copied from
|
||||
the eth2sp1 open-source project (github.com/jochemvdmeulen/eth2sp1),
|
||||
library file `hardware/SP1_eth2sp1_reference.kicad_mod`. Real purpose:
|
||||
hand-solder insert for J3 — J5 is fabricated on this same board/panel via
|
||||
a mouse-bite tab, snapped off after production, and soldered onto J3 so
|
||||
its gold fingers protrude past the board edge into the GC slot (J3 itself
|
||||
uses thru-hole insert pads, not bare gold fingers). Pad length tuned to
|
||||
13.5 mm + board thickness (1.1412 mm) = 14.6412 mm, then trimmed −1.0 mm to
|
||||
**13.6412 mm** (near/board-edge-side pad edge held fixed 0.6 mm off the
|
||||
nose throughout, matching eth2sp1's original tip clearance). J5 pins
|
||||
1,3–10 stay no-connect (DNP, no live signals); pins 2/11/12 (shield/ground)
|
||||
tie to a new **`EXI_GND`** net — a dedicated reference-plane net for the
|
||||
fingers, deliberately kept separate from board `GND` until physically
|
||||
joined to J3 by solder (J5 is a separate PCB fragment until then).
|
||||
- [x] Mouse-bite tab: 27× 0.4 mm NPTH holes at X=106.8900, spanning the
|
||||
full Y=48.1–66.6 tongue height (both endpoints landing on the
|
||||
original tongue corners as half-moon scallops) — footprint
|
||||
`MouseBites_J5`. **Has disappeared from the PCB and needed
|
||||
re-adding twice this session** (cause unknown — likely an
|
||||
accidental GUI selection/delete, watch for a third time).
|
||||
- [ ] **User is routing the `EXI_GND` reference plane + stitching vias
|
||||
under J5's fingers** — in progress, not finished. Guidance given:
|
||||
multiple vias per ground pad (not just one via per pin), plus
|
||||
stitching vias flanking the *signal* fingers (CLK/MOSI/MISO/CS)
|
||||
too, not just the 3 named ground pins — that's what actually
|
||||
controls impedance at the trace-to-finger transition.
|
||||
- [ ] J2's `HANRUN_HR911105A.kicad_mod` footprint has a cosmetic-only
|
||||
defect: pads 15/16 (2.445 mm ground/shield tabs) stick out ~0.97 mm
|
||||
past the F.Fab body-outline rectangle (top and bottom, symmetric).
|
||||
**Confirmed NOT a DRC/manufacturability issue** — the real courtyard
|
||||
(F.CrtYd) properly encloses both pads with ~0.28 mm margin; this is
|
||||
why JLCPCB's placement-preview render looked alarming (it draws the
|
||||
undersized F.Fab rectangle as the "body"). Offered to fix the F.Fab
|
||||
rectangle for cosmetic accuracy; not done.
|
||||
- **Gateware pin constraints — DONE** (was the "Write the re-bba-rb pin
|
||||
constraints" item below, now resolved): `exi_bba/synth.py`'s
|
||||
`IceBreakerPlatform` no longer targets the iCEbreaker — every pin pulled
|
||||
directly from the schematic netlist and verified placed by nextpnr.
|
||||
Also fixed two real bugs found in the process: **LED polarity was
|
||||
backwards** (D6/D7 are active-high on this board, opposite the
|
||||
iCEbreaker's onboard active-low LEDs the old code assumed) and **removed
|
||||
a reference to a physical button that doesn't exist on this board** (the
|
||||
iCEbreaker's `BTN_N` was dev-board-only; `panel_btn` now ties idle).
|
||||
- [x] **Real hardware conflict found and fixed**: the schematic originally
|
||||
put `ETH_INT` on U9 pin 35, which **physically conflicts with the
|
||||
iCE40UP5K's PLL hard macro** — pin 35 cannot be used as an *input*
|
||||
while the PLL is instantiated (confirmed both by nextpnr's own chip
|
||||
database and by direct testing: an unrelated input signal swapped
|
||||
onto pin 35 reproduces the identical conflict; an *output* signal
|
||||
on pin 35 works fine — the restriction is input-direction-specific,
|
||||
not a blanket "pin 35 is unusable"). Board was still in design, so
|
||||
fixed at the source: **`ETH_INT` moved from U9 pin 35 to pin 13**
|
||||
(schematic + PCB both reworked and verified — pin 13 was confirmed
|
||||
via icestorm's own pin database to be the *only* spare GPIO on this
|
||||
exact SG48 package/board combo; all other 38 usable pins were
|
||||
already assigned). PCB reroute done and DRC-clean (0 unconnected,
|
||||
0 shorts). An alternative (wr_n 36→35, rd_n 37→36, int_n→37, keeping
|
||||
ETH_INT physically clustered with the rest of the ethernet bus) was
|
||||
evaluated and rejected — it works but only found 1 passing seed out
|
||||
of 5 tried, with much thinner timing margin (0.4% vs 3%) than the
|
||||
pin-13 arrangement.
|
||||
- [x] **Timing verified — closes, seed-sensitive**: seed 1 narrowly missed
|
||||
(`capture_clk` 53.08 MHz vs 54.02 MHz target), seed 3 passes both
|
||||
domains cleanly (`clk` 37.82 MHz vs 24 MHz, `capture_clk` 55.69 MHz
|
||||
vs 54.02 MHz) — consistent with this design's known seed-sensitivity
|
||||
(routing-dominated at ~22% LC utilization). `build/top.bin` on disk
|
||||
is the seed-3 result. Re-verified after the PCB reroute — identical
|
||||
numbers, as expected (PCB copper doesn't affect FPGA-internal
|
||||
timing).
|
||||
- [ ] **Known bug, not fixed**: `synth.py`'s built-in `--seeds N` sweep
|
||||
loop throws silent exceptions on seeds after the first when run in
|
||||
one process (pre-existing, unrelated to this session's pin changes)
|
||||
— worked around by invoking each seed as a separate process. The
|
||||
convenience one-command multi-seed workflow needs debugging if
|
||||
wanted again.
|
||||
|
||||
## Critical — ALL RESOLVED (schematic + PCB, verified 2026-07-18)
|
||||
|
||||
- [x] **EXI DO/DI swapped at J3 — FIXED 2026-07-17** (all copper unchanged).
|
||||
@@ -72,19 +191,21 @@ remaining work is the Functional/Broader/ordering lists below.
|
||||
|
||||
## Functional / robustness
|
||||
|
||||
- [ ] **iceprog pin mismatch — schematic FIXED 2026-07-18**: FLASH_CS moved
|
||||
ADBUS3→ADBUS4 (U8 pin 21), CDONE ACBUS1→ADBUS6 (pin 23), CRESET
|
||||
ACBUS0→ADBUS7 (pin 24) — now exactly stock iceprog / iCEbreaker
|
||||
- [x] **iceprog pin mismatch — schematic FIXED 2026-07-18, PCB rerouted**:
|
||||
FLASH_CS moved ADBUS3→ADBUS4 (U8 pin 21), CDONE ACBUS1→ADBUS6 (pin 23),
|
||||
CRESET ACBUS0→ADBUS7 (pin 24) — now exactly stock iceprog / iCEbreaker
|
||||
channel-A convention; old pins are NC. Pull-ups R11/R12 unchanged.
|
||||
- [ ] PCB: reroute the three lines to the new U8 pins (F8 shows the
|
||||
pad-net changes).
|
||||
Verified 2026-07-22: 0 DRC violations in the U8 pin area, 0 unconnected
|
||||
items board-wide.
|
||||
- [x] **TPS2116 PR1 divider margin — FIXED 2026-07-18**: R3 200k→150k
|
||||
(0402WGF1503TCE, LCSC C25755). PR1 = 1.32 V nominal; switchover at
|
||||
GC_3V3 = 2.30–2.70 V worst-case — safely below the 3.3 V rail. (Value
|
||||
change only, same footprint — no PCB work.)
|
||||
- [ ] **ETH_RST pull-up — schematic FIXED 2026-07-18**: R36 10 k (C25744)
|
||||
from ETH_RST to **ETH_3V3** (low when ETH rail off).
|
||||
- [ ] PCB: place/route R36 near U11 pin 48.
|
||||
- [x] **ETH_RST pull-up — schematic FIXED 2026-07-18, PCB placed/routed**:
|
||||
R36 10 k (C25744) from ETH_RST to **ETH_3V3** (low when ETH rail off),
|
||||
at (148.49, 61.7225) near U11 pin 48. Verified 2026-07-22: nets
|
||||
`/ethernet/ETH_RST` + `/ethernet/ETH_3V3` both present on the footprint,
|
||||
0 unconnected items.
|
||||
- [ ] **Gateware: gate all outputs on GC_ON** — when GC_ON=0 the W5100S is
|
||||
unpowered (U12) and the GC is off, but FPGA banks stay at 3.3 V. Hold
|
||||
the W5100S bus and EXI outputs Hi-Z/low to avoid back-powering.
|
||||
@@ -93,41 +214,88 @@ remaining work is the Functional/Broader/ordering lists below.
|
||||
board PCF.
|
||||
- [ ] **Gateware: EXI INT drive style** — prefer open-drain emulation (drive
|
||||
low / release) on J3.3 rather than push-pull high.
|
||||
- [ ] **New 2026-07-22: 2 GND vias short the `/Power/3V3` zone on In2.Cu** —
|
||||
found during the last DRC pass, 4 error-severity violations (2×
|
||||
`clearance` + 2× `hole_clearance`, both 0 mm actual). Two GND vias at
|
||||
(190.78, 58.58) and (190.34, 58.58) — just south of J3's courtyard,
|
||||
likely stitching vias added during the J3 reroute — sit directly on
|
||||
top of the 3V3 pour on In2.Cu. This is a real short risk, not a
|
||||
manufacturability nit: move or delete these two vias (or void the 3V3
|
||||
zone locally) before ordering. Also 1 harmless `track_dangling`: a
|
||||
0.06 mm stub on `/exi/EXI_MOSI_RAW` near (188.39, 57.52) — routing
|
||||
debris, delete when convenient.
|
||||
|
||||
## Broader items (beyond the wiring review — block fab on the first two)
|
||||
|
||||
- [ ] **Write the re-bba-rb pin constraints** — `exi_bba/synth.py` still targets
|
||||
the iCEbreaker. Full board pin map: EXI_MOSI = 4 (IOB_8a, in),
|
||||
EXI_MISO = 3 (IOB_9b, out), EXI_CLK = 44 (G6), EXI_CS = 45,
|
||||
EXI_INT = 46; W5100S bus on the IOT bank (23–43); CLK12 = 20 (G3);
|
||||
GC_ON = 21; ETH_RST = 2; UART: FPGA RX = 18 (net UART_TXD!, FTDI
|
||||
output), FPGA TX = 19; **debug: LED_G = 47 (heartbeat), LED_R = 48
|
||||
(EXI activity), DBG0–4 = 9/10/11/12/6 (J4 header)**. Pure software;
|
||||
do before ordering to prove the pinout.
|
||||
- [x] **Write the re-bba-rb pin constraints — DONE 2026-07-24**, see the
|
||||
"Status 2026-07-24" note at the top for full details. Real board pin
|
||||
map: EXI_MOSI = 4 (IOB_8a, in), EXI_MISO = 3 (IOB_9b, out),
|
||||
EXI_CLK = 44 (G6), EXI_CS = 45, EXI_INT = 46; W5100S bus A0=42 A1=38
|
||||
D0-D7=34/32/31/28/27/26/25/23 CS_N=43 RD_N=37 WR_N=36 RST_N=2;
|
||||
**ETH_INT moved from the schematic's original pin 35 to pin 13** (pin
|
||||
35 physically conflicts with the PLL for input use — hardware
|
||||
constraint, not fixable in software, resolved via schematic+PCB
|
||||
rework since the board was still in design); CLK12 = 20 (G3);
|
||||
UART: FPGA RX = 18 (net UART_TXD!, FTDI output), FPGA TX = 19;
|
||||
debug: LED_G = 47 (heartbeat, active-high), LED_R = 48 (EXI activity,
|
||||
active-high), DBG0–4 = 9/10/11/12/6 (J4 header). No physical button
|
||||
on this board — the old iCEbreaker BTN_N reference was removed.
|
||||
Placement + timing verified (nextpnr, seed 3: clk 37.82 MHz/24 target,
|
||||
capture_clk 55.69 MHz/54.02 target, both PASS).
|
||||
- [ ] **Debug provisions — schematic DONE 2026-07-18** (was: board had none):
|
||||
- D6 green heartbeat LED (Everlight 19-217/GHC-YR1S2/3T, C72043,
|
||||
Basic) on FPGA pin 47 (LED_G) via R37 330 Ω (C25104);
|
||||
- D6 green heartbeat LED (**Hubei KENTO KT-0603G, C12624** — swapped
|
||||
2026-07-24, Everlight original was out of stock) on FPGA pin 47
|
||||
(LED_G) via R37 **49.9 Ω** (C25120, swapped from 330 Ω same day to
|
||||
compensate for KT-0603G's higher Vf — see the 2026-07-24 status note);
|
||||
- D7 red EXI-activity LED (KENTO KT-0603R, C2286, Basic) on pin 48
|
||||
(LED_R) via R38;
|
||||
(LED_R) via R38 (unchanged, this one was never out of stock);
|
||||
- J4 6-pin debug header (unpopulated, in_bom no): GND + DBG0–4 =
|
||||
FPGA pins 9/10/11/12/6 — route EXI CLK/CS/MOSI/MISO copies here in
|
||||
gateware for logic-analyzer bring-up;
|
||||
- TP1 3V3, TP2 1V2, TP3 ETH_3V3 (ethernet sheet), TP4 GC_ON, TP5 GND
|
||||
(1.5 mm pads, in_bom no);
|
||||
- FID1–3 fiducials placed directly on the PCB (board-only) at
|
||||
(195, 68.5)/(131, 48)/(163, 44.5) — copper-clear, DRC 0.
|
||||
- [ ] PCB: place/route the 11 schematic footprints (D6/D7, R36/R37/
|
||||
R38, TP1–5, J4) — F8 pulls them in. LEDs need visibility with
|
||||
the GC shell on: place near the RJ45/USB edge if possible.
|
||||
- [ ] **Verify mechanical fit** (bench item — cannot be verified in repo):
|
||||
outline vs the SP1 slot, RJ45/USB-C protrusion vs the GC serial port
|
||||
bay opening. An earlier commit says "need to remeasure PCB outline".
|
||||
Note 2026-07-18: the J3 footprint (12 contacts, 1 mm effective pitch,
|
||||
two staggered depth rows, front-side only, fingers to the board edge
|
||||
per the .kicad_dru exception) is the geometry derived from the
|
||||
physical sp1_test_plug iterations — the test-plug project itself
|
||||
contains no reusable finger footprint to diff against, so the
|
||||
provenance is the physical test, not a file comparison.
|
||||
- FID1–3 fiducials: **superseded 2026-07-22**, see the fiducials entry
|
||||
under "JLCPCB ordering notes" below for current footprint/positions.
|
||||
- [x] **PCB: place/route the 11 schematic footprints — DONE**, verified
|
||||
2026-07-22: D6/D7/R37/R38/TP1–5/J4 all present with correct net
|
||||
assignments (`Net-(D6-A)`/`Net-(D7-A)`/`/fpga/LED_G`/`/fpga/LED_R`
|
||||
for the LEDs, `/Power/3V3`/`/fpga/1V2`/`/ethernet/ETH_3V3`/
|
||||
`/GC_ON`/`GND` for TP1–5, `/fpga/DBG0-4`+`GND` for J4), 0
|
||||
unconnected items. LED visibility vs the GC shell not
|
||||
re-verified here (bench item).
|
||||
- [x] **Verify mechanical fit — major progress 2026-07-22** (bench item,
|
||||
photo-based, this session): the user measured the real GameCube SP1
|
||||
bay using an Android reference-square app (ImageMeter) against a 2 cm
|
||||
calibration square, photographing up into the bay with J2 (Ethernet
|
||||
jack) as the fixed anchor. Cross-referencing those measurements against
|
||||
the PCB's J3/J2 courtyards (courtyard, not pad or slot, is the correct
|
||||
mechanical reference) found J3 was mispositioned in Y by ~5 mm.
|
||||
Orientation (which real-world edge maps to which PCB edge) was
|
||||
independently confirmed via a numerical fit check (original pairing:
|
||||
~2–3 mm residual both sides; a candidate 180°-about-X-axis reflection
|
||||
was tested and rejected: 6.3 mm residual on one side) plus a rendered
|
||||
PCB PDF sanity check.
|
||||
- [x] **J3 shifted**: `(at 189.85 59.9)` → `(at 189.85 54.9)`, i.e.
|
||||
**Y −5.0 mm**, X unchanged (X was checked against both bay edges
|
||||
using the board's true front/back edges — no shift needed). J3
|
||||
was fully unrouted at shift time (0 track segments touched any
|
||||
of its 24 pads, verified beforehand) so the move was electrically
|
||||
free; the resulting 183 DRC collisions (D2 + EXI_* net clearances
|
||||
in the new J3 footprint area) have since been resolved by
|
||||
rerouting — 0 J3-area DRC errors remain as of 2026-07-22, and J3
|
||||
is now fully routed (see above).
|
||||
- [ ] X/Y still not verified against real hardware — this was a
|
||||
photo/measurement-based correction, not a fit-check against an
|
||||
actual GameCube. Confirm on the bench when a unit is available.
|
||||
- [ ] Insertion depth (Z, connector engagement into the slot) —
|
||||
explicitly deferred by the user, not addressed this pass.
|
||||
- Note 2026-07-18 (unchanged): the J3 footprint (12 contacts, 1 mm
|
||||
effective pitch, two staggered depth rows, front-side only,
|
||||
fingers to the board edge per the .kicad_dru exception) is the
|
||||
geometry derived from the physical sp1_test_plug iterations —
|
||||
the test-plug project itself contains no reusable finger
|
||||
footprint to diff against, so the provenance is the physical
|
||||
test, not a file comparison.
|
||||
- [x] **SP1 12 V rail viability — VERIFIED against existing projects
|
||||
(2026-07-17).** webhdx's IDE-EXI v2 for Serial Port 1 (which became the
|
||||
commercial M.2 Loader): "New switching power regulator supplies 3.3V@2A
|
||||
@@ -197,10 +365,12 @@ remaining work is the Functional/Broader/ordering lists below.
|
||||
pin-compatible, but treat as a bring-up suspect if EXI ESD behaviour
|
||||
looks odd. C65 is an SMD electrolytic (Lelon VZH101M1ETR-0607, 25 V) —
|
||||
assembly-friendly, not THT as first assumed.
|
||||
- [ ] Fiducials: VERIFIED ABSENT (0 on the board, 2026-07-18). JLCPCB can
|
||||
panel-add their own, but 3 board fiducials (1 mm copper dot, 2 mm mask
|
||||
opening, asymmetric corners) is the robust choice — add with the debug
|
||||
LEDs/test points pass.
|
||||
- [x] Fiducials: **placed 2026-07-22** — `Fiducial_0.5mm_Mask1mm` (0.5 mm
|
||||
copper dot, 1 mm mask opening; downsized from the originally-planned
|
||||
1 mm/2 mm footprint because no spot on the real board had >5 mm
|
||||
clearance from other parts) at FID1 (160.0, 50.5), FID2 (184.2, 61.0),
|
||||
FID3 (187.3, 47.5) — asymmetric placement, all verified genuinely
|
||||
on-board against the true (non-bounding-box) board polygon, DRC 0.
|
||||
|
||||
## Housekeeping (repo) — done 2026-07-17
|
||||
|
||||
|
||||
@@ -11798,7 +11798,7 @@
|
||||
)
|
||||
)
|
||||
)
|
||||
(property "MPN" "0402WGF1002TCE"
|
||||
(property "MPN" "RC0402FR-0710KL"
|
||||
(at -77.47 -77.47 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
@@ -11809,7 +11809,7 @@
|
||||
)
|
||||
)
|
||||
)
|
||||
(property "Manufacturer" "UNI-ROYAL"
|
||||
(property "Manufacturer" "YAGEO"
|
||||
(at -77.47 -77.47 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
@@ -11820,7 +11820,7 @@
|
||||
)
|
||||
)
|
||||
)
|
||||
(property "LCSC" "C25744"
|
||||
(property "LCSC" "C60490"
|
||||
(at -77.47 -77.47 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
|
||||
@@ -9415,7 +9415,7 @@
|
||||
)
|
||||
)
|
||||
)
|
||||
(property "MPN" "0402WGF1002TCE"
|
||||
(property "MPN" "RC0402FR-0710KL"
|
||||
(at 0 0 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
@@ -9426,7 +9426,7 @@
|
||||
)
|
||||
)
|
||||
)
|
||||
(property "Manufacturer" "UNI-ROYAL"
|
||||
(property "Manufacturer" "YAGEO"
|
||||
(at 0 0 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
@@ -9437,7 +9437,7 @@
|
||||
)
|
||||
)
|
||||
)
|
||||
(property "LCSC" "C25744"
|
||||
(property "LCSC" "C60490"
|
||||
(at 0 0 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
|
||||
@@ -1239,10 +1239,46 @@
|
||||
(embedded_fonts no)
|
||||
)
|
||||
)
|
||||
(no_connect
|
||||
(at 110.49 90.17)
|
||||
(uuid "01aed343-ee55-43ca-9d12-da07db63d213")
|
||||
)
|
||||
(no_connect
|
||||
(at 110.49 85.09)
|
||||
(uuid "2e2bbfb5-a908-4239-8dea-edf46f2663e7")
|
||||
)
|
||||
(no_connect
|
||||
(at 110.49 95.25)
|
||||
(uuid "368adb60-1f1b-4962-9592-468333e9a431")
|
||||
)
|
||||
(no_connect
|
||||
(at 110.49 97.79)
|
||||
(uuid "40142202-21fa-4f5a-a288-f2919aa8a958")
|
||||
)
|
||||
(no_connect
|
||||
(at 110.49 77.47)
|
||||
(uuid "474ac82a-129d-48a0-999c-ba722f9c922d")
|
||||
)
|
||||
(no_connect
|
||||
(at 110.49 87.63)
|
||||
(uuid "4adfedad-c278-4598-814f-b739c90ab29f")
|
||||
)
|
||||
(no_connect
|
||||
(at 74.93 93.98)
|
||||
(uuid "b855de1b-54c4-47f5-a83c-8776d2aea575")
|
||||
)
|
||||
(no_connect
|
||||
(at 110.49 92.71)
|
||||
(uuid "bdb944a3-7209-41cd-a72e-20674055f3d3")
|
||||
)
|
||||
(no_connect
|
||||
(at 110.49 82.55)
|
||||
(uuid "cd245ba5-932c-42ce-967b-527cd3fbace9")
|
||||
)
|
||||
(no_connect
|
||||
(at 110.49 100.33)
|
||||
(uuid "f6478aab-b777-458a-8a20-38b2badd0941")
|
||||
)
|
||||
(wire
|
||||
(pts
|
||||
(xy 64.77 96.52) (xy 62.23 96.52)
|
||||
@@ -1255,7 +1291,7 @@
|
||||
)
|
||||
(wire
|
||||
(pts
|
||||
(xy 96.52 76.2) (xy 96.52 82.55)
|
||||
(xy 24.13 81.28) (xy 24.13 87.63)
|
||||
)
|
||||
(stroke
|
||||
(width 0)
|
||||
@@ -1285,7 +1321,7 @@
|
||||
)
|
||||
(wire
|
||||
(pts
|
||||
(xy 96.52 90.17) (xy 96.52 95.25)
|
||||
(xy 24.13 95.25) (xy 24.13 100.33)
|
||||
)
|
||||
(stroke
|
||||
(width 0)
|
||||
@@ -1383,6 +1419,16 @@
|
||||
)
|
||||
(uuid "a9b98f12-4996-44d1-ae46-2792ac2046f7")
|
||||
)
|
||||
(wire
|
||||
(pts
|
||||
(xy 38.1 95.25) (xy 38.1 100.33)
|
||||
)
|
||||
(stroke
|
||||
(width 0)
|
||||
(type default)
|
||||
)
|
||||
(uuid "aac1f9b8-1a7f-432f-a761-de465b824eee")
|
||||
)
|
||||
(wire
|
||||
(pts
|
||||
(xy 74.93 93.98) (xy 62.23 93.98)
|
||||
@@ -1393,6 +1439,16 @@
|
||||
)
|
||||
(uuid "ac10f016-ef9e-402a-8ae0-3b78bd758afa")
|
||||
)
|
||||
(wire
|
||||
(pts
|
||||
(xy 38.1 81.28) (xy 38.1 87.63)
|
||||
)
|
||||
(stroke
|
||||
(width 0)
|
||||
(type default)
|
||||
)
|
||||
(uuid "bdb465b5-698e-4fe3-95e6-abb757bdacf8")
|
||||
)
|
||||
(wire
|
||||
(pts
|
||||
(xy 74.93 81.28) (xy 62.23 81.28)
|
||||
@@ -1424,7 +1480,7 @@
|
||||
(uuid "fd73b349-d700-4bfa-9b20-b662f3b5fa69")
|
||||
)
|
||||
(label "EXI_MOSI_RAW"
|
||||
(at 27.94 90.17 180)
|
||||
(at 58.42 41.91 180)
|
||||
(effects
|
||||
(font
|
||||
(size 1.27 1.27)
|
||||
@@ -1434,7 +1490,7 @@
|
||||
(uuid "1673f89a-b196-4e3a-8b31-50ae5115685e")
|
||||
)
|
||||
(label "EXI_MISO_RAW"
|
||||
(at 27.94 85.09 180)
|
||||
(at 58.42 36.83 180)
|
||||
(effects
|
||||
(font
|
||||
(size 1.27 1.27)
|
||||
@@ -1453,8 +1509,18 @@
|
||||
)
|
||||
(uuid "2f6a1b3c-2b9e-4f1b-9d6a-6e8f4b0c1a2d")
|
||||
)
|
||||
(label "EXI_GND"
|
||||
(at 110.49 102.87 0)
|
||||
(effects
|
||||
(font
|
||||
(size 1.27 1.27)
|
||||
)
|
||||
(justify left)
|
||||
)
|
||||
(uuid "3847a147-ee7d-469e-b10b-cde365952105")
|
||||
)
|
||||
(label "EXI_INT"
|
||||
(at 27.94 97.79 180)
|
||||
(at 58.42 49.53 180)
|
||||
(effects
|
||||
(font
|
||||
(size 1.27 1.27)
|
||||
@@ -1474,7 +1540,7 @@
|
||||
(uuid "5b8c3d1e-6f7a-4b9c-9d0e-1f2a3b4c5d6e")
|
||||
)
|
||||
(label "EXI_CS"
|
||||
(at 27.94 87.63 180)
|
||||
(at 58.42 39.37 180)
|
||||
(effects
|
||||
(font
|
||||
(size 1.27 1.27)
|
||||
@@ -1514,17 +1580,17 @@
|
||||
(uuid "9e1d4a2b-8c3f-4a5e-b1d6-2f7c9e0a4b3d")
|
||||
)
|
||||
(label "12V_EXI"
|
||||
(at 46.99 86.36 180)
|
||||
(at 38.1 81.28 90)
|
||||
(effects
|
||||
(font
|
||||
(size 1.27 1.27)
|
||||
)
|
||||
(justify right bottom)
|
||||
(justify left bottom)
|
||||
)
|
||||
(uuid "a5f89a25-304f-4bd7-ad04-bee13500abd8")
|
||||
)
|
||||
(label "EXTIN_RAW"
|
||||
(at 27.94 95.25 180)
|
||||
(at 58.42 46.99 180)
|
||||
(effects
|
||||
(font
|
||||
(size 1.27 1.27)
|
||||
@@ -1543,8 +1609,18 @@
|
||||
)
|
||||
(uuid "c9d70ab0-2af1-490e-becd-c3978fe3fe26")
|
||||
)
|
||||
(label "EXI_GND"
|
||||
(at 110.49 80.01 0)
|
||||
(effects
|
||||
(font
|
||||
(size 1.27 1.27)
|
||||
)
|
||||
(justify left)
|
||||
)
|
||||
(uuid "d5e4c212-9d51-4b55-aa22-2e4e349b029c")
|
||||
)
|
||||
(label "EXI_CLK_RAW"
|
||||
(at 27.94 92.71 180)
|
||||
(at 58.42 44.45 180)
|
||||
(effects
|
||||
(font
|
||||
(size 1.27 1.27)
|
||||
@@ -1553,9 +1629,19 @@
|
||||
)
|
||||
(uuid "db4a6fbe-2eeb-435c-a6e4-0d2a028a1373")
|
||||
)
|
||||
(label "EXI_GND"
|
||||
(at 110.49 105.41 0)
|
||||
(effects
|
||||
(font
|
||||
(size 1.27 1.27)
|
||||
)
|
||||
(justify left)
|
||||
)
|
||||
(uuid "efd00d77-7e87-45bb-8c02-f9c931994a36")
|
||||
)
|
||||
(hierarchical_label "12V_EXI"
|
||||
(shape output)
|
||||
(at 96.52 76.2 90)
|
||||
(at 24.13 81.28 90)
|
||||
(effects
|
||||
(font
|
||||
(size 1.27 1.27)
|
||||
@@ -1707,7 +1793,7 @@
|
||||
)
|
||||
(symbol
|
||||
(lib_id "Device:C_Polarized")
|
||||
(at 96.52 86.36 0)
|
||||
(at 24.13 91.44 0)
|
||||
(unit 1)
|
||||
(body_style 1)
|
||||
(exclude_from_sim no)
|
||||
@@ -1717,7 +1803,7 @@
|
||||
(dnp no)
|
||||
(uuid "11c5a587-7b43-454b-8483-cecc6ffb0da5")
|
||||
(property "Reference" "C65"
|
||||
(at 99.06 85.09 0)
|
||||
(at 26.67 90.17 0)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
(effects
|
||||
@@ -1728,7 +1814,7 @@
|
||||
)
|
||||
)
|
||||
(property "Value" "100uF"
|
||||
(at 99.06 87.63 0)
|
||||
(at 26.67 92.71 0)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
(effects
|
||||
@@ -1739,7 +1825,7 @@
|
||||
)
|
||||
)
|
||||
(property "Footprint" "Capacitor_SMD:CP_Elec_6.3x7.7"
|
||||
(at 96.52 86.36 0)
|
||||
(at 24.13 91.44 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
@@ -1750,7 +1836,7 @@
|
||||
)
|
||||
)
|
||||
(property "Datasheet" ""
|
||||
(at 96.52 86.36 0)
|
||||
(at 24.13 91.44 0)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
(effects
|
||||
@@ -1760,7 +1846,7 @@
|
||||
)
|
||||
)
|
||||
(property "Description" "Polarized capacitor"
|
||||
(at 96.52 86.36 0)
|
||||
(at 24.13 91.44 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
@@ -1771,7 +1857,7 @@
|
||||
)
|
||||
)
|
||||
(property "MPN" "VZH101M1ETR-0607"
|
||||
(at 0 0 0)
|
||||
(at -72.39 5.08 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
@@ -1782,7 +1868,7 @@
|
||||
)
|
||||
)
|
||||
(property "Manufacturer" "Lelon"
|
||||
(at 0 0 0)
|
||||
(at -72.39 5.08 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
@@ -1793,7 +1879,7 @@
|
||||
)
|
||||
)
|
||||
(property "LCSC" "C311617"
|
||||
(at 0 0 0)
|
||||
(at -72.39 5.08 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
@@ -1804,7 +1890,7 @@
|
||||
)
|
||||
)
|
||||
(property "Type" "Aluminum"
|
||||
(at 96.52 86.36 0)
|
||||
(at 24.13 91.44 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
@@ -1815,7 +1901,7 @@
|
||||
)
|
||||
)
|
||||
(property "V" "25V"
|
||||
(at 96.52 86.36 0)
|
||||
(at 24.13 91.44 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
@@ -1842,7 +1928,7 @@
|
||||
)
|
||||
(symbol
|
||||
(lib_id "PUSB3AB6Z_ES:PUSB3AB6Z_ES")
|
||||
(at 38.1 91.44 0)
|
||||
(at 68.58 43.18 0)
|
||||
(unit 1)
|
||||
(body_style 1)
|
||||
(exclude_from_sim no)
|
||||
@@ -1852,7 +1938,7 @@
|
||||
(dnp no)
|
||||
(uuid "165499df-6aee-4ac7-8721-5c64a577f026")
|
||||
(property "Reference" "D2"
|
||||
(at 27.94 79.6698 0)
|
||||
(at 58.42 31.4098 0)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
(effects
|
||||
@@ -1863,7 +1949,7 @@
|
||||
)
|
||||
)
|
||||
(property "Value" "PUSB3AB6Z(ES)"
|
||||
(at 27.94 101.6 0)
|
||||
(at 58.42 53.34 0)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
(effects
|
||||
@@ -1874,7 +1960,7 @@
|
||||
)
|
||||
)
|
||||
(property "Footprint" "hardware:SON50P110X213X50-7"
|
||||
(at 38.1 91.44 0)
|
||||
(at 68.58 43.18 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
@@ -1885,7 +1971,7 @@
|
||||
)
|
||||
)
|
||||
(property "Datasheet" "https://assets.nexperia.com/documents/data-sheet/PUSB3AB6.pdf"
|
||||
(at 38.1 91.44 0)
|
||||
(at 68.58 43.18 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
@@ -1896,7 +1982,7 @@
|
||||
)
|
||||
)
|
||||
(property "Description" "6-channel 3.3V 0.15pF ultra-low-cap TVS array on EXI_CLK/CS/MOSI/MISO/INT + ExtIn, all channels used; tapped upstream of series resistors on the connector side"
|
||||
(at 38.1 91.44 0)
|
||||
(at 68.58 43.18 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
@@ -1907,7 +1993,7 @@
|
||||
)
|
||||
)
|
||||
(property "MPN" "PUSB3AB6Z(ES)"
|
||||
(at 38.1 91.44 0)
|
||||
(at 68.58 43.18 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
@@ -1918,7 +2004,7 @@
|
||||
)
|
||||
)
|
||||
(property "Manufacturer" "ElecSuper (2nd source of Nexperia PUSB3AB6Z)"
|
||||
(at 38.1 91.44 0)
|
||||
(at 68.58 43.18 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
@@ -1929,7 +2015,7 @@
|
||||
)
|
||||
)
|
||||
(property "LCSC" "C49383400"
|
||||
(at 38.1 91.44 0)
|
||||
(at 68.58 43.18 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
@@ -2044,6 +2130,117 @@
|
||||
)
|
||||
)
|
||||
)
|
||||
(symbol
|
||||
(lib_id "GameCube:Sp1_Connector")
|
||||
(at 109.22 90.17 0)
|
||||
(unit 1)
|
||||
(body_style 1)
|
||||
(exclude_from_sim no)
|
||||
(in_bom no)
|
||||
(on_board yes)
|
||||
(in_pos_files yes)
|
||||
(dnp yes)
|
||||
(uuid "20452aa5-87af-4da4-8d33-0ef66ad5d3a1")
|
||||
(property "Reference" "J5"
|
||||
(at 97.79 73.406 0)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
(effects
|
||||
(font
|
||||
(size 1.27 1.27)
|
||||
)
|
||||
(justify left)
|
||||
)
|
||||
)
|
||||
(property "Value" "SP1_REFERENCE_DNP"
|
||||
(at 96.52 75.692 0)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
(effects
|
||||
(font
|
||||
(size 1.27 1.27)
|
||||
)
|
||||
(justify left)
|
||||
)
|
||||
)
|
||||
(property "Footprint" "hardware:SP1_eth2sp1_reference"
|
||||
(at 110.49 74.93 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
(effects
|
||||
(font
|
||||
(size 1.27 1.27)
|
||||
)
|
||||
)
|
||||
)
|
||||
(property "Datasheet" ""
|
||||
(at 110.49 74.93 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
(effects
|
||||
(font
|
||||
(size 1.27 1.27)
|
||||
)
|
||||
)
|
||||
)
|
||||
(property "Description" "SP1 gold-finger insert, copied from eth2sp1 (github.com/jochemvdmeulen/eth2sp1). Fabricated on this panel via mouse-bite tab, snapped off and hand-soldered onto J3. Signal/power pins (1,3-10) are no-connect (mechanical/electrical bring-up happens after hand-soldering); pins 2,11,12 (shield/ground) tie to EXI_GND, a dedicated reference-plane net for the fingers, kept separate from board GND until joined to J3 by solder. Always DNP (bare PCB copper, not a purchasable part)."
|
||||
(at 110.49 74.93 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
(effects
|
||||
(font
|
||||
(size 1.27 1.27)
|
||||
)
|
||||
)
|
||||
)
|
||||
(pin "1"
|
||||
(uuid "59f0562f-32cd-4c7e-8927-a6c6a05f76fc")
|
||||
)
|
||||
(pin "2"
|
||||
(uuid "5b7a0a5d-c019-4f77-9e52-64adf18b75a2")
|
||||
)
|
||||
(pin "3"
|
||||
(uuid "2cda2185-1344-41ae-9d93-6deff5ea9bcc")
|
||||
)
|
||||
(pin "4"
|
||||
(uuid "142fdbd2-0221-454e-8c59-95a54d5aac6c")
|
||||
)
|
||||
(pin "5"
|
||||
(uuid "7fea9a74-d917-4b9e-9dcf-54493e2b2768")
|
||||
)
|
||||
(pin "6"
|
||||
(uuid "938d1a3f-b581-4bd2-86b8-5d5a8c794fe2")
|
||||
)
|
||||
(pin "7"
|
||||
(uuid "c9c4eee6-76ac-45d9-827e-309a8b734e92")
|
||||
)
|
||||
(pin "8"
|
||||
(uuid "0a0570c4-6206-4ea6-93dd-18503b43a38f")
|
||||
)
|
||||
(pin "9"
|
||||
(uuid "53b291ab-eac4-4987-94c1-3254b4199fed")
|
||||
)
|
||||
(pin "10"
|
||||
(uuid "3652d701-3638-4a18-8bdb-a84a8e6057fb")
|
||||
)
|
||||
(pin "11"
|
||||
(uuid "837a1ed3-35bf-4afc-a586-b44fd1ee0205")
|
||||
)
|
||||
(pin "12"
|
||||
(uuid "9e906f82-5998-4a2c-924d-47cc63fc4ad0")
|
||||
)
|
||||
(instances
|
||||
(project "re-bba-rb"
|
||||
(path "/dbb182a6-d579-468e-b98b-6f0950da9e3a/1b071f68-b4ea-469c-942f-de06380c9077"
|
||||
(reference "J5")
|
||||
(unit 1)
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
(symbol
|
||||
(lib_id "Device:R")
|
||||
(at 68.58 88.9 90)
|
||||
@@ -2222,7 +2419,7 @@
|
||||
)
|
||||
)
|
||||
)
|
||||
(property "MPN" "0402WGF1002TCE"
|
||||
(property "MPN" "RC0402FR-0710KL"
|
||||
(at 0 0 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
@@ -2233,7 +2430,7 @@
|
||||
)
|
||||
)
|
||||
)
|
||||
(property "Manufacturer" "UNI-ROYAL"
|
||||
(property "Manufacturer" "YAGEO"
|
||||
(at 0 0 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
@@ -2244,7 +2441,7 @@
|
||||
)
|
||||
)
|
||||
)
|
||||
(property "LCSC" "C25744"
|
||||
(property "LCSC" "C60490"
|
||||
(at 0 0 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
@@ -2396,7 +2593,7 @@
|
||||
)
|
||||
(symbol
|
||||
(lib_id "power:GND")
|
||||
(at 54.61 86.36 0)
|
||||
(at 38.1 100.33 0)
|
||||
(unit 1)
|
||||
(body_style 1)
|
||||
(exclude_from_sim no)
|
||||
@@ -2406,7 +2603,7 @@
|
||||
(dnp no)
|
||||
(uuid "48052d59-dcf9-4791-9862-00c7a87de3b8")
|
||||
(property "Reference" "#PWR0tvs12v01"
|
||||
(at 58.42 86.36 0)
|
||||
(at 41.91 100.33 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
@@ -2417,7 +2614,7 @@
|
||||
)
|
||||
)
|
||||
(property "Value" "GND"
|
||||
(at 55.372 86.36 0)
|
||||
(at 38.1 104.394 0)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
(effects
|
||||
@@ -2427,7 +2624,7 @@
|
||||
)
|
||||
)
|
||||
(property "Footprint" ""
|
||||
(at 54.61 86.36 0)
|
||||
(at 38.1 100.33 0)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
(effects
|
||||
@@ -2437,7 +2634,7 @@
|
||||
)
|
||||
)
|
||||
(property "Datasheet" ""
|
||||
(at 54.61 86.36 0)
|
||||
(at 38.1 100.33 0)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
(effects
|
||||
@@ -2447,7 +2644,7 @@
|
||||
)
|
||||
)
|
||||
(property "Description" "Power symbol creates a global label with name \"GND\" , ground"
|
||||
(at 54.61 86.36 0)
|
||||
(at 38.1 100.33 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
@@ -2546,7 +2743,7 @@
|
||||
)
|
||||
(symbol
|
||||
(lib_id "power:GND")
|
||||
(at 38.1 105.41 0)
|
||||
(at 68.58 57.15 0)
|
||||
(unit 1)
|
||||
(body_style 1)
|
||||
(exclude_from_sim no)
|
||||
@@ -2556,7 +2753,7 @@
|
||||
(dnp no)
|
||||
(uuid "5526d125-8107-4dba-85ca-4b5826ea8f92")
|
||||
(property "Reference" "#PWR0tvs01"
|
||||
(at 41.91 105.41 0)
|
||||
(at 72.39 57.15 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
@@ -2567,7 +2764,7 @@
|
||||
)
|
||||
)
|
||||
(property "Value" "GND"
|
||||
(at 38.862 105.41 0)
|
||||
(at 69.342 57.15 0)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
(effects
|
||||
@@ -2577,7 +2774,7 @@
|
||||
)
|
||||
)
|
||||
(property "Footprint" ""
|
||||
(at 38.1 105.41 0)
|
||||
(at 68.58 57.15 0)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
(effects
|
||||
@@ -2587,7 +2784,7 @@
|
||||
)
|
||||
)
|
||||
(property "Datasheet" ""
|
||||
(at 38.1 105.41 0)
|
||||
(at 68.58 57.15 0)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
(effects
|
||||
@@ -2597,7 +2794,7 @@
|
||||
)
|
||||
)
|
||||
(property "Description" "Power symbol creates a global label with name \"GND\" , ground"
|
||||
(at 38.1 105.41 0)
|
||||
(at 68.58 57.15 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
@@ -2918,7 +3115,7 @@
|
||||
)
|
||||
(symbol
|
||||
(lib_id "power:GND")
|
||||
(at 96.52 95.25 0)
|
||||
(at 24.13 100.33 0)
|
||||
(unit 1)
|
||||
(body_style 1)
|
||||
(exclude_from_sim no)
|
||||
@@ -2928,7 +3125,7 @@
|
||||
(dnp no)
|
||||
(uuid "ef19b682-da4b-4509-b903-3029f0beaedf")
|
||||
(property "Reference" "#PWR0d01"
|
||||
(at 96.52 99.06 0)
|
||||
(at 24.13 104.14 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
@@ -2939,7 +3136,7 @@
|
||||
)
|
||||
)
|
||||
(property "Value" "GND"
|
||||
(at 96.52 99.314 0)
|
||||
(at 24.13 104.394 0)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
(effects
|
||||
@@ -2949,7 +3146,7 @@
|
||||
)
|
||||
)
|
||||
(property "Footprint" ""
|
||||
(at 96.52 95.25 0)
|
||||
(at 24.13 100.33 0)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
(effects
|
||||
@@ -2959,7 +3156,7 @@
|
||||
)
|
||||
)
|
||||
(property "Datasheet" ""
|
||||
(at 96.52 95.25 0)
|
||||
(at 24.13 100.33 0)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
(effects
|
||||
@@ -2969,7 +3166,7 @@
|
||||
)
|
||||
)
|
||||
(property "Description" "Power symbol creates a global label with name \"GND\" , ground"
|
||||
(at 96.52 95.25 0)
|
||||
(at 24.13 100.33 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
@@ -2993,7 +3190,7 @@
|
||||
)
|
||||
(symbol
|
||||
(lib_id "Device:D_Zener")
|
||||
(at 50.8 86.36 0)
|
||||
(at 38.1 91.44 270)
|
||||
(unit 1)
|
||||
(body_style 1)
|
||||
(exclude_from_sim no)
|
||||
@@ -3003,7 +3200,7 @@
|
||||
(dnp no)
|
||||
(uuid "f1ace983-18bf-4781-be5e-b6b0e761dbc3")
|
||||
(property "Reference" "D3"
|
||||
(at 50.8 82.55 0)
|
||||
(at 41.91 91.44 0)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
(effects
|
||||
@@ -3013,7 +3210,7 @@
|
||||
)
|
||||
)
|
||||
(property "Value" "SMAJ12A"
|
||||
(at 50.8 90.17 0)
|
||||
(at 34.29 91.44 0)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
(effects
|
||||
@@ -3023,7 +3220,7 @@
|
||||
)
|
||||
)
|
||||
(property "Footprint" "Diode_SMD:D_SMA"
|
||||
(at 50.8 86.36 0)
|
||||
(at 38.1 91.44 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
@@ -3034,7 +3231,7 @@
|
||||
)
|
||||
)
|
||||
(property "Datasheet" ""
|
||||
(at 50.8 86.36 0)
|
||||
(at 38.1 91.44 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
@@ -3045,7 +3242,7 @@
|
||||
)
|
||||
)
|
||||
(property "Description" "12V unidirectional TVS, 400W (10/1000us), clamps 12V_EXI (SP1 pin 5) against surge/ESD; K (cathode) to rail, A (anode) to GND"
|
||||
(at 50.8 86.36 0)
|
||||
(at 38.1 91.44 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
@@ -3056,7 +3253,7 @@
|
||||
)
|
||||
)
|
||||
(property "MPN" "SMAJ12A"
|
||||
(at 50.8 86.36 0)
|
||||
(at 38.1 91.44 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
@@ -3067,7 +3264,7 @@
|
||||
)
|
||||
)
|
||||
(property "Manufacturer" "Hongjiacheng"
|
||||
(at 50.8 86.36 0)
|
||||
(at 38.1 91.44 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
@@ -3078,7 +3275,7 @@
|
||||
)
|
||||
)
|
||||
(property "LCSC" "C19077531"
|
||||
(at 50.8 86.36 0)
|
||||
(at 38.1 91.44 0)
|
||||
(hide yes)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
|
||||
@@ -1,6 +1,5 @@
|
||||
(fp_lib_table
|
||||
(version 7)
|
||||
(lib (name "gc") (type "KiCad") (uri "${KIPRJMOD}/gc.pretty") (options "") (descr ""))
|
||||
(lib (name "hardware") (type "KiCad") (uri "${KIPRJMOD}/..") (options "") (descr ""))
|
||||
(lib (name "sp1_test_plug") (type "KiCad") (uri "${KIPRJMOD}/../sp1_test_plug") (options "") (descr ""))
|
||||
)
|
||||
|
||||
+9486
-6146
File diff suppressed because it is too large
Load Diff
@@ -543,6 +543,25 @@
|
||||
"via_drill": 0.3,
|
||||
"wire_width": 6
|
||||
},
|
||||
{
|
||||
"bus_width": 12,
|
||||
"clearance": 0.15,
|
||||
"diff_pair_gap": 0.25,
|
||||
"diff_pair_via_gap": 0.25,
|
||||
"diff_pair_width": 0.2,
|
||||
"line_style": 0,
|
||||
"microvia_diameter": 0.3,
|
||||
"microvia_drill": 0.1,
|
||||
"name": "LED",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"priority": 1,
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.15,
|
||||
"tuning_profile": "",
|
||||
"via_diameter": 0.6,
|
||||
"via_drill": 0.3,
|
||||
"wire_width": 6
|
||||
},
|
||||
{
|
||||
"bus_width": 12,
|
||||
"clearance": 0.15,
|
||||
@@ -687,6 +706,50 @@
|
||||
{
|
||||
"netclass": "USB_DP",
|
||||
"pattern": "*FT_DN*"
|
||||
},
|
||||
{
|
||||
"netclass": "LED",
|
||||
"pattern": "/fpga/LED_G"
|
||||
},
|
||||
{
|
||||
"netclass": "LED",
|
||||
"pattern": "/fpga/LED_R"
|
||||
},
|
||||
{
|
||||
"netclass": "LED",
|
||||
"pattern": "*D6-A*"
|
||||
},
|
||||
{
|
||||
"netclass": "LED",
|
||||
"pattern": "*D7-A*"
|
||||
},
|
||||
{
|
||||
"netclass": "LED",
|
||||
"pattern": "*D8-A*"
|
||||
},
|
||||
{
|
||||
"netclass": "LED",
|
||||
"pattern": "*D8-K*"
|
||||
},
|
||||
{
|
||||
"netclass": "LED",
|
||||
"pattern": "*D9-A*"
|
||||
},
|
||||
{
|
||||
"netclass": "LED",
|
||||
"pattern": "*D11-K*"
|
||||
},
|
||||
{
|
||||
"netclass": "LED",
|
||||
"pattern": "*D12-K*"
|
||||
},
|
||||
{
|
||||
"netclass": "LED",
|
||||
"pattern": "*D13-K*"
|
||||
},
|
||||
{
|
||||
"netclass": "LED",
|
||||
"pattern": "*Q2-C*"
|
||||
}
|
||||
]
|
||||
},
|
||||
|
||||
@@ -1239,7 +1239,7 @@
|
||||
)
|
||||
(sheet
|
||||
(at 189.23 96.52)
|
||||
(size 34.925 61.976)
|
||||
(size 34.925 51.435)
|
||||
(exclude_from_sim no)
|
||||
(in_bom yes)
|
||||
(on_board yes)
|
||||
@@ -1265,7 +1265,7 @@
|
||||
)
|
||||
)
|
||||
(property "Sheetfile" "ethernet.kicad_sch"
|
||||
(at 189.23 159.0806 0)
|
||||
(at 189.23 148.5396 0)
|
||||
(show_name no)
|
||||
(do_not_autoplace no)
|
||||
(effects
|
||||
|
||||
Reference in New Issue
Block a user