Finished the board including the connector and mousebites
This commit is contained in:
Dennis Brentjes
+207
-37
@@ -6,6 +6,125 @@ manufacturing limits. Status 2026-07-18: **all three critical findings fixed
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in schematic AND PCB** (ERC 0, DRC 0 errors / 0 unconnected / 0 parity);
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remaining work is the Functional/Broader/ordering lists below.
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**Status 2026-07-22 (last-check pass):** ERC still clean (2 known-benign
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`lib_symbol_issues` on the generic Q_NPN_BEC/Q_PNP_BEC library symbols, not
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real problems). DRC: 0 unconnected items board-wide (incl. J3 — all 24 pads
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now carry real net copper, confirmed by direct pad/net inspection, not just
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the ratsnest count); 242 total violations, of which only **4 are errors**
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(2× `clearance` + 2× `hole_clearance`, two GND vias at (190.78/190.34, 58.58)
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0 mm from the `/Power/3V3` zone on In2.Cu — see Functional/robustness below),
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1 `track_dangling` (a 0.06 mm stub on `/exi/EXI_MOSI_RAW` near (188.39,
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57.52), likely harmless routing debris), and the rest are silkscreen
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warnings (171 overlap, 60 over-copper, 6 edge-clearance). This session also
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did extensive photo-based mechanical verification and a real J3 Y-position
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correction — see "Verify mechanical fit" below — and re-added fiducials with
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a different footprint/position than this file previously documented.
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**Status 2026-07-24 (major session):** ERC 0 (same 2 known-benign warnings +
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1 expected `power_pin_not_driven` on J5's `EXI_GND`, see below — not a real
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problem, that net has no power-symbol driver by design). DRC: 0 unconnected
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items, 280 total violations — same silkscreen-warning baseline as before
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plus `npth_inside_courtyard` (27, J5's mouse-bite holes sit close to J2's
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courtyard, judged benign — holes, not a component body) and 1 harmless
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`track_dangling`. The 2 GND-vias-vs-3V3-zone short from 2026-07-22 is
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**gone** (resolved somewhere in this session's PCB work, confirmed via fresh
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DRC). Gerbers/BOM/CPL all regenerated and verified current as of this pass.
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Major work this session:
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- **D6/D8/D9/D12 green LEDs swapped** Everlight 19-217/GHC-YR1S2/3T (C72043,
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out of stock) → Hubei KENTO KT-0603G (C12624) — same 0603 footprint, same
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manufacturer family as the already-used red KT-0603R (D7/D11). Series
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resistors R37/R41/R42 changed 330 Ω → **49.9 Ω** (reused C25120, the same
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part already on R26–R29 — no new BOM line) to compensate for KT-0603G's
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higher Vf (3.1 V typ.) and restore comparable brightness (~4 mA vs the
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~0.6 mA the old resistor value would have given it). D12/D13 (RGB channels,
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driven directly by the FPGA's `SB_RGBA_DRV` hard macro, no series resistor)
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need no resistor change — flagged as slightly reduced current-source
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headroom at the higher Vf, not fixed (nothing to fix, no resistor exists).
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- [ ] **D13 (yellow, Everlight C72038) and the 10 kΩ 0402 resistor
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(UNI-ROYAL C25744, used by 12 designators) are ALSO reported out of
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stock** — real in-stock alternatives were being researched
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(candidates: Hubei KENTO KT-0603Y/KT-0805Y for D13; YAGEO
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RC0402FR-0710KL C60490 or Vishay CRCW040210K0FKED C71617 for the
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10k) but never confirmed/committed — stock claims from web search
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proved unreliable earlier this session (contradicted by direct
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JLCPCB part-page checks twice), so these need a live stock check
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before ordering, same as the green LED did.
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- **J5 added**: a second SP1 gold-finger connector, footprint copied from
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the eth2sp1 open-source project (github.com/jochemvdmeulen/eth2sp1),
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library file `hardware/SP1_eth2sp1_reference.kicad_mod`. Real purpose:
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hand-solder insert for J3 — J5 is fabricated on this same board/panel via
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a mouse-bite tab, snapped off after production, and soldered onto J3 so
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its gold fingers protrude past the board edge into the GC slot (J3 itself
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uses thru-hole insert pads, not bare gold fingers). Pad length tuned to
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13.5 mm + board thickness (1.1412 mm) = 14.6412 mm, then trimmed −1.0 mm to
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**13.6412 mm** (near/board-edge-side pad edge held fixed 0.6 mm off the
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nose throughout, matching eth2sp1's original tip clearance). J5 pins
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1,3–10 stay no-connect (DNP, no live signals); pins 2/11/12 (shield/ground)
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tie to a new **`EXI_GND`** net — a dedicated reference-plane net for the
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fingers, deliberately kept separate from board `GND` until physically
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joined to J3 by solder (J5 is a separate PCB fragment until then).
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- [x] Mouse-bite tab: 27× 0.4 mm NPTH holes at X=106.8900, spanning the
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full Y=48.1–66.6 tongue height (both endpoints landing on the
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original tongue corners as half-moon scallops) — footprint
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`MouseBites_J5`. **Has disappeared from the PCB and needed
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re-adding twice this session** (cause unknown — likely an
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accidental GUI selection/delete, watch for a third time).
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- [ ] **User is routing the `EXI_GND` reference plane + stitching vias
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under J5's fingers** — in progress, not finished. Guidance given:
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multiple vias per ground pad (not just one via per pin), plus
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stitching vias flanking the *signal* fingers (CLK/MOSI/MISO/CS)
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too, not just the 3 named ground pins — that's what actually
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controls impedance at the trace-to-finger transition.
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- [ ] J2's `HANRUN_HR911105A.kicad_mod` footprint has a cosmetic-only
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defect: pads 15/16 (2.445 mm ground/shield tabs) stick out ~0.97 mm
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past the F.Fab body-outline rectangle (top and bottom, symmetric).
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**Confirmed NOT a DRC/manufacturability issue** — the real courtyard
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(F.CrtYd) properly encloses both pads with ~0.28 mm margin; this is
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why JLCPCB's placement-preview render looked alarming (it draws the
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undersized F.Fab rectangle as the "body"). Offered to fix the F.Fab
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rectangle for cosmetic accuracy; not done.
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- **Gateware pin constraints — DONE** (was the "Write the re-bba-rb pin
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constraints" item below, now resolved): `exi_bba/synth.py`'s
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`IceBreakerPlatform` no longer targets the iCEbreaker — every pin pulled
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directly from the schematic netlist and verified placed by nextpnr.
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Also fixed two real bugs found in the process: **LED polarity was
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backwards** (D6/D7 are active-high on this board, opposite the
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iCEbreaker's onboard active-low LEDs the old code assumed) and **removed
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a reference to a physical button that doesn't exist on this board** (the
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iCEbreaker's `BTN_N` was dev-board-only; `panel_btn` now ties idle).
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- [x] **Real hardware conflict found and fixed**: the schematic originally
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put `ETH_INT` on U9 pin 35, which **physically conflicts with the
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iCE40UP5K's PLL hard macro** — pin 35 cannot be used as an *input*
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while the PLL is instantiated (confirmed both by nextpnr's own chip
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database and by direct testing: an unrelated input signal swapped
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onto pin 35 reproduces the identical conflict; an *output* signal
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on pin 35 works fine — the restriction is input-direction-specific,
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not a blanket "pin 35 is unusable"). Board was still in design, so
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fixed at the source: **`ETH_INT` moved from U9 pin 35 to pin 13**
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(schematic + PCB both reworked and verified — pin 13 was confirmed
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via icestorm's own pin database to be the *only* spare GPIO on this
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exact SG48 package/board combo; all other 38 usable pins were
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already assigned). PCB reroute done and DRC-clean (0 unconnected,
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0 shorts). An alternative (wr_n 36→35, rd_n 37→36, int_n→37, keeping
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ETH_INT physically clustered with the rest of the ethernet bus) was
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evaluated and rejected — it works but only found 1 passing seed out
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of 5 tried, with much thinner timing margin (0.4% vs 3%) than the
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pin-13 arrangement.
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- [x] **Timing verified — closes, seed-sensitive**: seed 1 narrowly missed
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(`capture_clk` 53.08 MHz vs 54.02 MHz target), seed 3 passes both
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domains cleanly (`clk` 37.82 MHz vs 24 MHz, `capture_clk` 55.69 MHz
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vs 54.02 MHz) — consistent with this design's known seed-sensitivity
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(routing-dominated at ~22% LC utilization). `build/top.bin` on disk
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is the seed-3 result. Re-verified after the PCB reroute — identical
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numbers, as expected (PCB copper doesn't affect FPGA-internal
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timing).
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- [ ] **Known bug, not fixed**: `synth.py`'s built-in `--seeds N` sweep
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loop throws silent exceptions on seeds after the first when run in
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one process (pre-existing, unrelated to this session's pin changes)
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— worked around by invoking each seed as a separate process. The
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convenience one-command multi-seed workflow needs debugging if
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wanted again.
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## Critical — ALL RESOLVED (schematic + PCB, verified 2026-07-18)
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- [x] **EXI DO/DI swapped at J3 — FIXED 2026-07-17** (all copper unchanged).
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@@ -72,19 +191,21 @@ remaining work is the Functional/Broader/ordering lists below.
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## Functional / robustness
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- [ ] **iceprog pin mismatch — schematic FIXED 2026-07-18**: FLASH_CS moved
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ADBUS3→ADBUS4 (U8 pin 21), CDONE ACBUS1→ADBUS6 (pin 23), CRESET
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ACBUS0→ADBUS7 (pin 24) — now exactly stock iceprog / iCEbreaker
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- [x] **iceprog pin mismatch — schematic FIXED 2026-07-18, PCB rerouted**:
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FLASH_CS moved ADBUS3→ADBUS4 (U8 pin 21), CDONE ACBUS1→ADBUS6 (pin 23),
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CRESET ACBUS0→ADBUS7 (pin 24) — now exactly stock iceprog / iCEbreaker
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channel-A convention; old pins are NC. Pull-ups R11/R12 unchanged.
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- [ ] PCB: reroute the three lines to the new U8 pins (F8 shows the
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pad-net changes).
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Verified 2026-07-22: 0 DRC violations in the U8 pin area, 0 unconnected
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items board-wide.
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- [x] **TPS2116 PR1 divider margin — FIXED 2026-07-18**: R3 200k→150k
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(0402WGF1503TCE, LCSC C25755). PR1 = 1.32 V nominal; switchover at
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GC_3V3 = 2.30–2.70 V worst-case — safely below the 3.3 V rail. (Value
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change only, same footprint — no PCB work.)
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- [ ] **ETH_RST pull-up — schematic FIXED 2026-07-18**: R36 10 k (C25744)
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from ETH_RST to **ETH_3V3** (low when ETH rail off).
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- [ ] PCB: place/route R36 near U11 pin 48.
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- [x] **ETH_RST pull-up — schematic FIXED 2026-07-18, PCB placed/routed**:
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R36 10 k (C25744) from ETH_RST to **ETH_3V3** (low when ETH rail off),
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at (148.49, 61.7225) near U11 pin 48. Verified 2026-07-22: nets
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`/ethernet/ETH_RST` + `/ethernet/ETH_3V3` both present on the footprint,
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0 unconnected items.
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- [ ] **Gateware: gate all outputs on GC_ON** — when GC_ON=0 the W5100S is
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unpowered (U12) and the GC is off, but FPGA banks stay at 3.3 V. Hold
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the W5100S bus and EXI outputs Hi-Z/low to avoid back-powering.
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@@ -93,41 +214,88 @@ remaining work is the Functional/Broader/ordering lists below.
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board PCF.
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- [ ] **Gateware: EXI INT drive style** — prefer open-drain emulation (drive
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low / release) on J3.3 rather than push-pull high.
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- [ ] **New 2026-07-22: 2 GND vias short the `/Power/3V3` zone on In2.Cu** —
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found during the last DRC pass, 4 error-severity violations (2×
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`clearance` + 2× `hole_clearance`, both 0 mm actual). Two GND vias at
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(190.78, 58.58) and (190.34, 58.58) — just south of J3's courtyard,
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likely stitching vias added during the J3 reroute — sit directly on
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top of the 3V3 pour on In2.Cu. This is a real short risk, not a
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manufacturability nit: move or delete these two vias (or void the 3V3
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zone locally) before ordering. Also 1 harmless `track_dangling`: a
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0.06 mm stub on `/exi/EXI_MOSI_RAW` near (188.39, 57.52) — routing
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debris, delete when convenient.
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## Broader items (beyond the wiring review — block fab on the first two)
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- [ ] **Write the re-bba-rb pin constraints** — `exi_bba/synth.py` still targets
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the iCEbreaker. Full board pin map: EXI_MOSI = 4 (IOB_8a, in),
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EXI_MISO = 3 (IOB_9b, out), EXI_CLK = 44 (G6), EXI_CS = 45,
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EXI_INT = 46; W5100S bus on the IOT bank (23–43); CLK12 = 20 (G3);
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GC_ON = 21; ETH_RST = 2; UART: FPGA RX = 18 (net UART_TXD!, FTDI
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output), FPGA TX = 19; **debug: LED_G = 47 (heartbeat), LED_R = 48
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(EXI activity), DBG0–4 = 9/10/11/12/6 (J4 header)**. Pure software;
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do before ordering to prove the pinout.
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- [x] **Write the re-bba-rb pin constraints — DONE 2026-07-24**, see the
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"Status 2026-07-24" note at the top for full details. Real board pin
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map: EXI_MOSI = 4 (IOB_8a, in), EXI_MISO = 3 (IOB_9b, out),
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EXI_CLK = 44 (G6), EXI_CS = 45, EXI_INT = 46; W5100S bus A0=42 A1=38
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D0-D7=34/32/31/28/27/26/25/23 CS_N=43 RD_N=37 WR_N=36 RST_N=2;
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**ETH_INT moved from the schematic's original pin 35 to pin 13** (pin
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35 physically conflicts with the PLL for input use — hardware
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constraint, not fixable in software, resolved via schematic+PCB
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rework since the board was still in design); CLK12 = 20 (G3);
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UART: FPGA RX = 18 (net UART_TXD!, FTDI output), FPGA TX = 19;
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debug: LED_G = 47 (heartbeat, active-high), LED_R = 48 (EXI activity,
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active-high), DBG0–4 = 9/10/11/12/6 (J4 header). No physical button
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on this board — the old iCEbreaker BTN_N reference was removed.
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Placement + timing verified (nextpnr, seed 3: clk 37.82 MHz/24 target,
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capture_clk 55.69 MHz/54.02 target, both PASS).
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- [ ] **Debug provisions — schematic DONE 2026-07-18** (was: board had none):
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- D6 green heartbeat LED (Everlight 19-217/GHC-YR1S2/3T, C72043,
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Basic) on FPGA pin 47 (LED_G) via R37 330 Ω (C25104);
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- D6 green heartbeat LED (**Hubei KENTO KT-0603G, C12624** — swapped
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2026-07-24, Everlight original was out of stock) on FPGA pin 47
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(LED_G) via R37 **49.9 Ω** (C25120, swapped from 330 Ω same day to
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compensate for KT-0603G's higher Vf — see the 2026-07-24 status note);
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- D7 red EXI-activity LED (KENTO KT-0603R, C2286, Basic) on pin 48
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(LED_R) via R38;
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(LED_R) via R38 (unchanged, this one was never out of stock);
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- J4 6-pin debug header (unpopulated, in_bom no): GND + DBG0–4 =
|
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FPGA pins 9/10/11/12/6 — route EXI CLK/CS/MOSI/MISO copies here in
|
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gateware for logic-analyzer bring-up;
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- TP1 3V3, TP2 1V2, TP3 ETH_3V3 (ethernet sheet), TP4 GC_ON, TP5 GND
|
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(1.5 mm pads, in_bom no);
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- FID1–3 fiducials placed directly on the PCB (board-only) at
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(195, 68.5)/(131, 48)/(163, 44.5) — copper-clear, DRC 0.
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- [ ] PCB: place/route the 11 schematic footprints (D6/D7, R36/R37/
|
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R38, TP1–5, J4) — F8 pulls them in. LEDs need visibility with
|
||||
the GC shell on: place near the RJ45/USB edge if possible.
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- [ ] **Verify mechanical fit** (bench item — cannot be verified in repo):
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outline vs the SP1 slot, RJ45/USB-C protrusion vs the GC serial port
|
||||
bay opening. An earlier commit says "need to remeasure PCB outline".
|
||||
Note 2026-07-18: the J3 footprint (12 contacts, 1 mm effective pitch,
|
||||
two staggered depth rows, front-side only, fingers to the board edge
|
||||
per the .kicad_dru exception) is the geometry derived from the
|
||||
physical sp1_test_plug iterations — the test-plug project itself
|
||||
contains no reusable finger footprint to diff against, so the
|
||||
provenance is the physical test, not a file comparison.
|
||||
- FID1–3 fiducials: **superseded 2026-07-22**, see the fiducials entry
|
||||
under "JLCPCB ordering notes" below for current footprint/positions.
|
||||
- [x] **PCB: place/route the 11 schematic footprints — DONE**, verified
|
||||
2026-07-22: D6/D7/R37/R38/TP1–5/J4 all present with correct net
|
||||
assignments (`Net-(D6-A)`/`Net-(D7-A)`/`/fpga/LED_G`/`/fpga/LED_R`
|
||||
for the LEDs, `/Power/3V3`/`/fpga/1V2`/`/ethernet/ETH_3V3`/
|
||||
`/GC_ON`/`GND` for TP1–5, `/fpga/DBG0-4`+`GND` for J4), 0
|
||||
unconnected items. LED visibility vs the GC shell not
|
||||
re-verified here (bench item).
|
||||
- [x] **Verify mechanical fit — major progress 2026-07-22** (bench item,
|
||||
photo-based, this session): the user measured the real GameCube SP1
|
||||
bay using an Android reference-square app (ImageMeter) against a 2 cm
|
||||
calibration square, photographing up into the bay with J2 (Ethernet
|
||||
jack) as the fixed anchor. Cross-referencing those measurements against
|
||||
the PCB's J3/J2 courtyards (courtyard, not pad or slot, is the correct
|
||||
mechanical reference) found J3 was mispositioned in Y by ~5 mm.
|
||||
Orientation (which real-world edge maps to which PCB edge) was
|
||||
independently confirmed via a numerical fit check (original pairing:
|
||||
~2–3 mm residual both sides; a candidate 180°-about-X-axis reflection
|
||||
was tested and rejected: 6.3 mm residual on one side) plus a rendered
|
||||
PCB PDF sanity check.
|
||||
- [x] **J3 shifted**: `(at 189.85 59.9)` → `(at 189.85 54.9)`, i.e.
|
||||
**Y −5.0 mm**, X unchanged (X was checked against both bay edges
|
||||
using the board's true front/back edges — no shift needed). J3
|
||||
was fully unrouted at shift time (0 track segments touched any
|
||||
of its 24 pads, verified beforehand) so the move was electrically
|
||||
free; the resulting 183 DRC collisions (D2 + EXI_* net clearances
|
||||
in the new J3 footprint area) have since been resolved by
|
||||
rerouting — 0 J3-area DRC errors remain as of 2026-07-22, and J3
|
||||
is now fully routed (see above).
|
||||
- [ ] X/Y still not verified against real hardware — this was a
|
||||
photo/measurement-based correction, not a fit-check against an
|
||||
actual GameCube. Confirm on the bench when a unit is available.
|
||||
- [ ] Insertion depth (Z, connector engagement into the slot) —
|
||||
explicitly deferred by the user, not addressed this pass.
|
||||
- Note 2026-07-18 (unchanged): the J3 footprint (12 contacts, 1 mm
|
||||
effective pitch, two staggered depth rows, front-side only,
|
||||
fingers to the board edge per the .kicad_dru exception) is the
|
||||
geometry derived from the physical sp1_test_plug iterations —
|
||||
the test-plug project itself contains no reusable finger
|
||||
footprint to diff against, so the provenance is the physical
|
||||
test, not a file comparison.
|
||||
- [x] **SP1 12 V rail viability — VERIFIED against existing projects
|
||||
(2026-07-17).** webhdx's IDE-EXI v2 for Serial Port 1 (which became the
|
||||
commercial M.2 Loader): "New switching power regulator supplies 3.3V@2A
|
||||
@@ -197,10 +365,12 @@ remaining work is the Functional/Broader/ordering lists below.
|
||||
pin-compatible, but treat as a bring-up suspect if EXI ESD behaviour
|
||||
looks odd. C65 is an SMD electrolytic (Lelon VZH101M1ETR-0607, 25 V) —
|
||||
assembly-friendly, not THT as first assumed.
|
||||
- [ ] Fiducials: VERIFIED ABSENT (0 on the board, 2026-07-18). JLCPCB can
|
||||
panel-add their own, but 3 board fiducials (1 mm copper dot, 2 mm mask
|
||||
opening, asymmetric corners) is the robust choice — add with the debug
|
||||
LEDs/test points pass.
|
||||
- [x] Fiducials: **placed 2026-07-22** — `Fiducial_0.5mm_Mask1mm` (0.5 mm
|
||||
copper dot, 1 mm mask opening; downsized from the originally-planned
|
||||
1 mm/2 mm footprint because no spot on the real board had >5 mm
|
||||
clearance from other parts) at FID1 (160.0, 50.5), FID2 (184.2, 61.0),
|
||||
FID3 (187.3, 47.5) — asymmetric placement, all verified genuinely
|
||||
on-board against the true (non-bounding-box) board polygon, DRC 0.
|
||||
|
||||
## Housekeeping (repo) — done 2026-07-17
|
||||
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Reference in New Issue
Block a user