Finished the board including the connector and mousebites

.claude/skills/kicad-manufacturing-export/SKILL.md

@@ -0,0 +1,134 @@
+---
+name: kicad-manufacturing-export
+description: Use when regenerating or exporting the BOM CSV, CPL/position CSV, or Gerbers+drill zip for a KiCad PCB project via kicad-cli (e.g. "regenerate the gerbers", "update the BOM and CPL", "re-export for JLCPCB"). Covers the exact kicad-cli invocations and column formats this project's ordering files expect, and the CPL rotation-correction trap (regenerating the position file the naive way silently wipes hand-verified assembly rotation fixes). KiCad 8/9/10, JLCPCB-style deliverables.
+---
+
+# Regenerating BOM / CPL / Gerbers via kicad-cli
+
+For the `re-bba-rb` board specifically, deliverables live in
+`hardware/re-bba-rb/`: `re-bba-rb-bom.csv`, `re-bba-rb-cpl.csv`,
+`gerbers/rebbarb.zip`. Adjust paths/output names for other boards, but the
+gotchas below (especially the CPL rotation trap) apply generally.
+
+## 1. Gerbers + drill + zip
+
+```bash
+cd hardware/re-bba-rb
+kicad-cli pcb export gerbers --board-plot-params -o gerbers/ re-bba-rb.kicad_pcb
+kicad-cli pcb export drill --format excellon --excellon-separate-th \
+  --excellon-units mm -o gerbers/ re-bba-rb.kicad_pcb
+```
+
+`--board-plot-params` reuses whatever layer/plot settings are already stored
+in the board file — don't hand-pick layers, this reproduces exactly what was
+there before. `--excellon-separate-th` splits plated/non-plated holes into
+`*-PTH.drl` / `*-NPTH.drl`, matching the existing file-naming convention.
+
+Then re-zip (excluding the previous zip itself, so it's not nested inside
+its own replacement):
+
+```python
+import zipfile, os
+folder = 'gerbers'
+files = sorted(f for f in os.listdir(folder) if f != 'rebbarb.zip')
+with zipfile.ZipFile(os.path.join(folder, 'rebbarb.zip'), 'w', zipfile.ZIP_DEFLATED) as z:
+    for f in files:
+        z.write(os.path.join(folder, f), arcname=f)
+```
+
+kicad-cli's gerber export also produces a `*-job.gbrjob` metadata file
+alongside the layer files — include it in the zip, it's harmless and some
+fabs use it for auto-configuration.
+
+## 2. BOM
+
+```bash
+kicad-cli sch export bom \
+  --fields "ITEM_NUMBER,Reference,Value,Footprint,MPN,LCSC,QUANTITY,DNP,Manufacturer" \
+  --labels "Item,Designator,Value,Footprint,MPN,LCSC,Qty,DNP,Manufacturer" \
+  --group-by "Value,Footprint,MPN,LCSC,Manufacturer" \
+  --sort-field "Reference" \
+  --ref-range-delimiter "" \
+  -o re-bba-rb-bom.csv \
+  re-bba-rb.kicad_sch
+```
+
+`--ref-range-delimiter ""` disables range compression (`C18-C20` becomes
+`C18,C19,C20`) — this project's existing BOM convention is flat comma lists,
+not ranges; drop this flag if the target format wants ranges instead.
+`--group-by` on those 5 fields means any two components sharing value +
+footprint + MPN + LCSC + manufacturer collapse into one row (with a combined
+`Qty`) — this is how e.g. adding a new part that happens to match an
+*already-used* part (same value/footprint/MPN) merges into an existing BOM
+line instead of creating a new one, which is usually what you want (no new
+line item added to the order).
+
+Reference-only / non-purchasable footprints (gold-finger connectors, mouse-bite
+NPTH-hole footprints, etc.) are excluded automatically via `in_bom no` on the
+schematic symbol (or `exclude_from_bom` in the footprint's `attr`) — don't
+try to filter them out in the export command itself.
+
+**Verify after export**: diff the new BOM against the old one and sanity-check
+that only expected rows changed — an unexpectedly *shorter* BOM (fewer
+component rows/refs than before) is the signature of the
+[kicad-bom-edit](../kicad-bom-edit/SKILL.md) skill's "malformed property
+silently drops a whole sheet" bug, not a real BOM change.
+
+## 3. CPL / position file — the rotation trap
+
+```bash
+kicad-cli pcb export pos --format csv --units mm --side both --exclude-dnp \
+  -o /tmp/pos_raw.csv re-bba-rb.kicad_pcb
+```
+
+kicad-cli's own CSV columns (`Ref,Val,Package,PosX,PosY,Rot,Side`) don't match
+JLCPCB's expected format (`Designator,Mid X,Mid Y,Layer,Rotation`, with
+`Layer` capitalized `Top`/`Bottom`, not lowercase `top`/`bottom`). Transform:
+
+```python
+import csv
+with open('/tmp/pos_raw.csv', newline='') as f:
+    rows = list(csv.DictReader(f))
+with open('re-bba-rb-cpl.csv', 'w', newline='') as f:
+    writer = csv.writer(f)
+    writer.writerow(['Designator', 'Mid X', 'Mid Y', 'Layer', 'Rotation'])
+    for r in rows:
+        layer = 'Top' if r['Side'].strip().lower() == 'top' else 'Bottom'
+        writer.writerow([r['Ref'], f"{float(r['PosX']):.6f}",
+                          f"{float(r['PosY']):.6f}", layer,
+                          f"{float(r['Rot']):.6f}"])
+```
+
+**Then — before treating this as done — reapply every correction in
+[`hardware/re-bba-rb/CPL_ROTATIONS.md`](../../../hardware/re-bba-rb/CPL_ROTATIONS.md).**
+KiCad's raw per-footprint rotation frequently does not match what the
+assembler expects (arbitrary per-footprint authoring reference vs. the
+assembler's actual placement convention), and this has already been
+hand-verified part-by-part against JLCPCB's placement-preview render for
+this board. Regenerating the position file "the normal way" silently
+overwrites those fixes back to (wrong) raw values — there is no automated
+check that catches this, so it's easy to quietly ship a regression. Read
+that file's sign-convention note before applying anything (short version:
+"N degrees clockwise" feedback means *subtract* N in the CPL's Y-up frame,
+not add it).
+
+Do **not** reach for a generic community rotation-correction table (e.g.
+`cpl_rotations_db.csv` from JLCKicadTools) as a shortcut — one was tried on
+this board and found wrong for at least one package family (claimed
+`LQFP-: 270°`; this board's actual correct value is 0°, unmodified). That
+table is calibrated against a specific plugin's own raw-rotation baseline,
+which is not the same as `kicad-cli`'s raw CSV baseline (different Y-axis
+handling) — the numbers don't transfer.
+
+## Quick full-refresh recipe
+
+1. Gerbers/drill/zip: regenerate + re-zip (section 1) — safe to always redo,
+   no hidden state to lose.
+2. BOM: regenerate (section 2) — safe to always redo. Diff-check the row
+   count.
+3. CPL: regenerate raw (section 3), **then reapply CPL_ROTATIONS.md** before
+   calling it current.
+4. Run ERC (`kicad-cli sch erc --severity-all`) and DRC
+   (`kicad-cli pcb drc --severity-all`) after any schematic/PCB change that
+   prompted the refresh — not the export step itself, but worth confirming
+   nothing regressed if this was bundled with other edits.

CLAUDE.md

@@ -254,7 +254,7 @@ plug (schematic, PCB, custom GameCube symbol library). Used to verify pad geomet
 before ordering the interposer PCB; not part of the FPGA build.
 
 `hardware/re-bba-rb/` — the actual adapter PCB (FT2232H + iCE40UP5K + W5100S,
-powered from SP1 12 V via buck). Two companion documents, both mandatory
+powered from SP1 12 V via buck). Three companion documents, all mandatory
 reading before touching this board:
 - **`hardware/re-bba-rb/TODO.md`** — open action items (what still needs doing:
   PCB placement of the 2026-07-18 fix parts, board PCF, bench checks, JLC
@@ -267,8 +267,16 @@ reading before touching this board:
   **Do not re-review or "fix" anything listed there without new evidence, and
   keep REVIEW.md updated in the same commit whenever a reviewed circuit
   changes or a new review is performed.**
+- **`hardware/re-bba-rb/CPL_ROTATIONS.md`** — per-part assembly rotation
+  corrections applied on top of `kicad-cli`'s raw CPL export (KiCad's raw
+  rotation frequently doesn't match what the assembler expects, and a
+  generic community correction table was tried and found wrong for this
+  board — do not reapply it). **Regenerating `re-bba-rb-cpl.csv` "the normal
+  way" silently wipes these corrections** — always reapply the corrections
+  in this file after any CPL regen, and read its confidence notes before
+  trusting any specific part's rotation.
 The authoritative board pin map (EXI, ETH bus, UART crossover, LED/DBG pins)
-is in both files; use it when writing the board PCF.
+is in TODO.md and REVIEW.md; use it when writing the board PCF.
 
 ---
 

exi_bba/bba_top.py

@@ -60,7 +60,9 @@ class BBATop(Elaboratable):
         # iCEbreaker — see synth.py).  panel_led bit order matches StatusPanel.
         self._status_panel = status_panel
         # Optional UART debug console (8N1 115200, sync domain).
-        # uart_tx → FT2232H Channel B pin 9; uart_rx ← pin 6.
+        # uart_tx → FT2232H Channel B (net UART_RXD, pin 19);
+        # uart_rx ← FT2232H Channel B (net UART_TXD, pin 18) — net names are
+        # FTDI-perspective, so this is not a naming mismatch, see synth.py.
         self._uart_console = uart_console
 
         # EXI (GC side)

exi_bba/synth.py

@@ -1,4 +1,4 @@
-"""Synthesis script for BBATop → iCEbreaker (iCE40UP5K SG48).
+"""Synthesis script for BBATop → re-bba-rb interposer board (iCE40UP5K SG48).
 
 Run from workspace root:
     python -m exi_bba.synth              # synthesize only
@@ -20,19 +20,43 @@ from exi_bba.bba_top import BBATop
 
 
 # ── Platform definition ───────────────────────────────────────────────────
-# Pin assignments use the iCEbreaker PMOD connectors as placeholders.
-# Replace with actual SP1-interposer pin numbers once PCB is finalised.
+# Real re-bba-rb board pin map, pulled directly from the schematic netlist
+# (U9 = iCE40UP5K-SG48ITR) — not iCEbreaker PMOD placeholders.
 #
-# PMOD1A (J2): pins 4 2 47 45 / 3 48 46 44  (top/bottom)
-# PMOD1B (J3): pins 43 38 34 31 / 42 36 32 28
-# PMOD2  (J4): pins 27 25 21 19 / 26 23 20 18
+# EXI (GC side)   : CLK=44(G6)  MOSI=4(IOB_8a)  MISO=3(IOB_9b)  CS=45  INT=46
+# W5100 bus (IOT bank, indirect parallel):
+#   A0=42  A1=38   D0=34 D1=32 D2=31 D3=28 D4=27 D5=26 D6=25 D7=23
+#   CS_N=43  RD_N=37  WR_N=36  RST_N=2 (net /ethernet/ETH_RST, NOT on the IOT
+#   bank — separate pin)
+# Board ties the W5100's upper address lines A[14:2] to 0 (only A[1:0]
+# wired); DATA[7:0] is bidirectional (SB_IO tristate, shared output-enable).
 #
-# EXI   : CLK=4  MOSI=2  MISO=47  CS_N=45  INT_N=3   (PMOD1A)
-# W5100 : indirect parallel bus — 15 pins across PMOD1B + PMOD2.
-#   ADDR[1:0]=43 38   DATA[7:0]=34 31 42 36 32 28 27 25
-#   CS_N=21  RD_N=19  WR_N=26  INT_N=23  RST_N=20      (pin 18 free)
-# Board: tie the W5100's upper address lines A[14:2] to 0 (only A[1:0] wired);
-# DATA[7:0] is bidirectional (SB_IO tristate, single shared output-enable).
+# INT_N=13 — MOVED off the schematic's original pin 35: pin 35 physically
+# conflicts with the iCE40UP5K's PLL hard macro (nextpnr: "PLL bel
+# 'X12/Y31/pll_3' cannot be used... conflicts with input... on pin 35"),
+# and this design needs the PLL for the 54 MHz capture-domain clock. Pin 35
+# cannot be used as regular I/O at all while the PLL is instantiated,
+# regardless of what drives it — this is a fixed silicon constraint, not a
+# routing choice. Pin 13 was picked because it's the ONLY spare GPIO on this
+# exact SG48 package/board combo: the 5k-sg48 package has 39 usable I/O pins
+# total (per icestorm's icebox.py pin database), and every other one is
+# already assigned to a real signal on this board — pin 13 shows up in the
+# schematic netlist as an unrouted U9 pad, nothing else was available.
+# Board is still in design, so PIN 13 ON THE SCHEMATIC/PCB MUST BE REWORKED
+# to carry ETH_INT instead of pin 35 before layout is final.
+#
+# Debug (J4 header, unpopulated): DBG0=9 DBG1=10 DBG2=11 DBG3=12 DBG4=6
+# UART (FT2232H channel B): net UART_TXD is the FTDI's OUTPUT, so it is the
+#   FPGA's RX input, and vice versa for UART_RXD — FPGA RX=18(UART_TXD net),
+#   FPGA TX=19(UART_RXD net). Do not swap by "TXD means transmit" instinct.
+# Status LEDs: D6(green,heartbeat)=LED_G=pin47, D7(red,EXI-activity)=LED_R=
+#   pin48 — both wired ACTIVE-HIGH (LED anode toward the FPGA pin via its
+#   series resistor, cathode to GND), unlike the iCEbreaker's own onboard
+#   LEDs which are active-low. No physical button exists on this board (the
+#   iCEbreaker's BTN_N was dev-board-only); panel_btn is tied idle instead.
+# RGB status LED (D11=red/rx, D12=green/tx, D13=yellow/ready) is on the
+#   iCE40UP5K's dedicated SB_RGBA_DRV pins 39/40/41 — fixed by the chip
+#   package on any board, not board-specific, so no resource needed here.
 
 class IceBreakerPlatform(LatticeICE40Platform):
     device      = "iCE40UP5K"
@@ -45,43 +69,38 @@ class IceBreakerPlatform(LatticeICE40Platform):
                  Clock(12e6),
                  Attrs(GLOBAL=True, IO_STANDARD="SB_LVCMOS")),
 
-        # EXI interface (GC side, SPI Mode 3) — PMOD1A FPGA pins
+        # EXI interface (GC side, SPI Mode 3)
         Resource("exi", 0,
-                 Subsignal("clk",   Pins("4",  dir="i")),
-                 Subsignal("mosi",  Pins("2",  dir="i")),
-                 Subsignal("miso",  Pins("47", dir="o")),
+                 Subsignal("clk",   Pins("44", dir="i")),
+                 Subsignal("mosi",  Pins("4",  dir="i")),
+                 Subsignal("miso",  Pins("3",  dir="o")),
                  Subsignal("cs_n",  Pins("45", dir="i")),
-                 Subsignal("int_n", Pins("3",  dir="o")),
+                 Subsignal("int_n", Pins("46", dir="o")),
                  Attrs(IO_STANDARD="SB_LVCMOS")),
 
-        # W5100 indirect parallel bus — PMOD1B + PMOD2 FPGA pins
+        # W5100 indirect parallel bus
         Resource("w5100", 0,
-                 Subsignal("addr",  Pins("43 38", dir="o")),
-                 Subsignal("data",  Pins("34 31 42 36 32 28 27 25", dir="io")),
-                 Subsignal("cs_n",  Pins("21", dir="o")),
-                 Subsignal("rd_n",  Pins("19", dir="o")),
-                 Subsignal("wr_n",  Pins("26", dir="o")),
-                 Subsignal("int_n", Pins("23", dir="i")),
-                 Subsignal("rst_n", Pins("18", dir="o")),
+                 Subsignal("addr",  Pins("42 38", dir="o")),
+                 Subsignal("data",  Pins("34 32 31 28 27 26 25 23", dir="io")),
+                 Subsignal("cs_n",  Pins("43", dir="o")),
+                 Subsignal("rd_n",  Pins("37", dir="o")),
+                 Subsignal("wr_n",  Pins("36", dir="o")),
+                 Subsignal("int_n", Pins("13", dir="i")),
+                 Subsignal("rst_n", Pins("2",  dir="o")),
                  Attrs(IO_STANDARD="SB_LVCMOS")),
 
-        # Bring-up status panel → iCEbreaker ONBOARD parts (dedicated pins, not
-        # on any PMOD, so they coexist with EXI + W5100).  LEDR/LEDG are
-        # active-low discrete LEDs; BTN_N is the user button.
-        # RGB LED (pins 39/40/41) is driven via SB_RGBA_DRV — not declared here
-        # as a platform resource (see BBATopSynth.elaborate, status_panel block).
-        Resource("ledr", 0, Pins("11", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS")),
-        Resource("ledg", 0, Pins("37", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS")),
-        Resource("btn",  0, Pins("10", dir="i"), Attrs(IO_STANDARD="SB_LVCMOS")),
+        # Bring-up status panel: D6/D7 discrete LEDs (active-high on this
+        # board). RGB (pins 39/40/41) is driven via SB_RGBA_DRV — not
+        # declared here as a platform resource (see BBATopSynth.elaborate).
+        # No onboard button on this board (see note above).
+        Resource("ledr", 0, Pins("48", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS")),
+        Resource("ledg", 0, Pins("47", dir="o"), Attrs(IO_STANDARD="SB_LVCMOS")),
 
-        # UART debug console → iCEbreaker FT2232H Channel B (onboard USB-UART).
-        # No external hardware needed — the FT2232H is already on the board.
+        # UART debug console → FT2232H Channel B.
         # On the PC: open the second USB serial port at 115200 8N1.
-        #   pin  9 = FPGA TX → FT2232H Channel B RX  (FPGA drives)
-        #   pin  6 = FPGA RX ← FT2232H Channel B TX  (FPGA reads)
         Resource("uart", 0,
-                 Subsignal("tx", Pins("9",  dir="o")),
-                 Subsignal("rx", Pins("6",  dir="i")),
+                 Subsignal("tx", Pins("19", dir="o")),
+                 Subsignal("rx", Pins("18", dir="i")),
                  Attrs(IO_STANDARD="SB_LVCMOS")),
     ]
 
@@ -124,23 +143,23 @@ class BBATopSynth(BBATop):
                 w5100.rst_n.o    .eq(self.w5100_rst_n),
             ]
 
-            # ── Bring-up status panel → onboard LEDs / button ──────────────
+            # ── Bring-up status panel → onboard LEDs ────────────────────────
             # All 5 panel LEDs mapped:
-            #   LEDG (pin 37)        = led[0] heartbeat
-            #   LEDR (pin 11)        = led[1] EXI activity
+            #   LEDG (pin 47) = led[0] heartbeat
+            #   LEDR (pin 48) = led[1] EXI activity
             #   RGB  (pins 39/40/41) = led[2] rx / led[3] tx / led[4] ready
-            # The one onboard button → panel btn[1] (manual re-init).
+            # No physical button on this board — panel_btn tied idle/released.
             if self._status_panel:
                 ledr = platform.request("ledr", 0)
                 ledg = platform.request("ledg", 0)
-                btn  = platform.request("btn",  0)
                 led  = self.panel_led
 
                 m.d.comb += [
-                    ledg.o.eq(~led[0]),     # heartbeat    (active-low LED)
-                    ledr.o.eq(~led[1]),     # EXI activity (active-low LED)
-                    # btn[0]/[2] held released (active-low idle = 1)
-                    self.panel_btn.eq(Cat(C(1, 1), btn.i, C(1, 1))),
+                    ledg.o.eq(led[0]),      # heartbeat    (active-high LED)
+                    ledr.o.eq(led[1]),      # EXI activity (active-high LED)
+                    # all 3 bits idle/released (active-low idle = 1) — no
+                    # physical button exists on this board to read
+                    self.panel_btn.eq(C(0b111, 3)),
                 ]
 
                 # iCEbreaker RGB LED has no series resistors — must use
@@ -205,26 +224,39 @@ if __name__ == "__main__":
             # versions; treat as non-fatal timing failure.
             print(f"  [seed {seed}] build exception (timing?): {exc}")
 
-        # Parse fmax from nextpnr log in build/top.tim (if present)
+        # Parse fmax from nextpnr log in build/top.tim (if present). Domain
+        # names are 'clk' (exi/sync, 24 MHz target) and 'capture_clk'
+        # (54 MHz target, the tighter constraint) — NOT 'exi', which never
+        # matched any real log line (this regex silently reported 0.0 MHz
+        # for every seed until fixed).
         import glob, re
         tim_files = glob.glob("build/top.tim") + glob.glob("build/*.tim")
-        fmax_exi = 0.0
+        fmax_clk = 0.0
+        fmax_capture = 0.0
         for tf in tim_files:
             try:
                 with open(tf) as f:
                     for line in f:
                         m_ = re.search(
-                            r"Max frequency.*exi.*?:\s*([\d.]+)\s*MHz", line)
+                            r"Max frequency for clock\s+'(\w+)':\s*([\d.]+)\s*MHz", line)
                         if m_:
-                            fmax_exi = float(m_.group(1))
+                            domain, freq = m_.group(1), float(m_.group(2))
+                            if domain == "clk":
+                                fmax_clk = freq
+                            elif domain == "capture_clk":
+                                fmax_capture = freq
             except OSError:
                 pass
-        print(f"  [seed {seed}] exi fmax extracted: {fmax_exi:.1f} MHz")
-        if fmax_exi > best_fmax:
-            best_fmax = fmax_exi
+        print(f"  [seed {seed}] clk fmax: {fmax_clk:.2f} MHz (target 24)  "
+              f"capture_clk fmax: {fmax_capture:.2f} MHz (target 54.02)")
+        # capture_clk is the binding constraint (tighter target, historically
+        # the one that swings ±20% with seed) — rank seeds by it.
+        if fmax_capture > best_fmax:
+            best_fmax = fmax_capture
             best_seed = seed
 
-    print(f"\nBest seed: {best_seed}  exi fmax: {best_fmax:.1f} MHz")
+    print(f"\nBest seed: {best_seed}  capture_clk fmax: {best_fmax:.2f} MHz "
+          f"(target 54.02) — {'PASS' if best_fmax >= 54.02 else 'FAIL'}")
 
     if do_flash:
         print(f"\nFlashing with seed {best_seed}...")

hardware/SP1_eth2sp1_reference.kicad_mod

@@ -0,0 +1,231 @@
+(footprint "SP1_eth2sp1_reference"
+	(version 20260206)
+	(generator "pcbnew")
+	(generator_version "10.0")
+	(layer "F.Cu")
+	(descr "SP1 gold-finger contact geometry from the eth2sp1 open-source project (github.com/jochemvdmeulen/eth2sp1) for visual/DRC reference comparison against this board's own J3. Pad length: eth2sp1's original 7mm, extended to 13.5mm + board thickness (1.1412mm) = 14.6412mm, then trimmed 1.0mm to 13.6412mm - anchored at the board-edge-proximal pad edge (0.6mm inboard of the nose, matching eth2sp1's original tip clearance) with all length changes taken from the far/inner edge. REFERENCE ONLY - not this board's actual connector (J3 uses hand-solder-insert thru-hole pads, not bare gold fingers). Always DNP. The small nose/edge outline is on Cmts.User (reference only, NOT Edge.Cuts) since a second disconnected Edge.Cuts fragment breaks the board's outline closure check.")
+	(tags "SP1 GameCube reference eth2sp1 DNP")
+	(property "Reference" "REF**"
+		(at 0 2 0)
+		(unlocked yes)
+		(layer "F.SilkS")
+		(uuid "340c217a-0562-4247-ace1-d31c792bb209")
+		(effects
+			(font
+				(size 1 1)
+				(thickness 0.15)
+			)
+		)
+	)
+	(property "Value" "SP1_eth2sp1_reference"
+		(at 0 4 0)
+		(unlocked yes)
+		(layer "F.Fab")
+		(uuid "8b032738-6eb1-429c-af4f-ba212781503c")
+		(effects
+			(font
+				(size 1 1)
+				(thickness 0.15)
+			)
+		)
+	)
+	(property "Footprint" "hardware:SP1_eth2sp1_reference"
+		(at 0 5 0)
+		(unlocked yes)
+		(layer "F.Fab")
+		(hide yes)
+		(uuid "25053893-94be-416c-9ba4-cce6dec782d2")
+		(effects
+			(font
+				(size 1 1)
+				(thickness 0.15)
+			)
+		)
+	)
+	(property "Datasheet" ""
+		(at 0 5 0)
+		(unlocked yes)
+		(layer "F.Fab")
+		(hide yes)
+		(uuid "87da103c-056f-4b3b-b875-aed40f5a5ce5")
+		(effects
+			(font
+				(size 1 1)
+				(thickness 0.15)
+			)
+		)
+	)
+	(property "Description" ""
+		(at 0 5 0)
+		(unlocked yes)
+		(layer "F.Fab")
+		(hide yes)
+		(uuid "f751e2dc-bf5b-41e2-a5bf-97f5433e2ed0")
+		(effects
+			(font
+				(size 1 1)
+				(thickness 0.15)
+			)
+		)
+	)
+	(fp_line
+		(start 6.5 -6.4)
+		(end 6.5 0)
+		(stroke
+			(width 0.1)
+			(type solid)
+		)
+		(layer "Cmts.User")
+		(uuid "a26abfe7-0d15-4f9d-86b0-59f940f6ed12")
+	)
+	(fp_line
+		(start 5.9 -7)
+		(end -5.9 -7)
+		(stroke
+			(width 0.1)
+			(type solid)
+		)
+		(layer "Cmts.User")
+		(uuid "fa1cc527-0999-43e3-bbee-4911cef99d9d")
+	)
+	(fp_line
+		(start -6.5 -6.4)
+		(end -6.5 0)
+		(stroke
+			(width 0.1)
+			(type solid)
+		)
+		(layer "Cmts.User")
+		(uuid "dfa6c775-2697-4bc0-98b5-4153a6dce288")
+	)
+	(fp_arc
+		(start 5.9 -7)
+		(mid 6.324264 -6.824264)
+		(end 6.5 -6.4)
+		(stroke
+			(width 0.1)
+			(type solid)
+		)
+		(layer "Cmts.User")
+		(uuid "eba98ff8-ca8d-4f65-b41f-361504a39c10")
+	)
+	(fp_arc
+		(start -6.5 -6.4)
+		(mid -6.324264 -6.824264)
+		(end -5.9 -7)
+		(stroke
+			(width 0.1)
+			(type solid)
+		)
+		(layer "Cmts.User")
+		(uuid "50917725-a0b9-4d21-8808-9d0fb16672aa")
+	)
+	(fp_text user "${REFERENCE}"
+		(at 0 2.5 0)
+		(unlocked yes)
+		(layer "F.Fab")
+		(uuid "5cedd119-6420-42e7-a09a-2282fd0981a7")
+		(effects
+			(font
+				(size 1 1)
+				(thickness 0.15)
+			)
+		)
+	)
+	(pad "1" smd rect
+		(at -5.5 0.4206 180)
+		(size 1.5 13.6412)
+		(layers "B.Cu" "B.Mask")
+		(pinfunction "EXTIN")
+		(pintype "input+no_connect")
+		(uuid "8160b939-ce92-4631-9852-2a26e1aea0cc")
+	)
+	(pad "2" smd rect
+		(at -4.5 0.4206 180)
+		(size 1.5 13.6412)
+		(layers "F.Cu" "F.Mask")
+		(pinfunction "GNDs")
+		(pintype "input")
+		(uuid "4dc936d5-4eb4-4ff3-9e33-5d98412966b1")
+	)
+	(pad "3" smd rect
+		(at -3.5 0.4206 180)
+		(size 1.5 13.6412)
+		(layers "B.Cu" "B.Mask")
+		(pinfunction "INT")
+		(pintype "input")
+		(uuid "4ed42ce0-553a-4c9f-b206-078ea82c1d06")
+	)
+	(pad "4" smd rect
+		(at -2.5 0.4206 180)
+		(size 1.5 13.6412)
+		(layers "F.Cu" "F.Mask")
+		(pinfunction "CLK")
+		(pintype "input")
+		(uuid "dbfb64b2-7d83-416d-9b70-f19bd0546f5b")
+	)
+	(pad "5" smd rect
+		(at -1.5 0.4206 180)
+		(size 1.5 13.6412)
+		(layers "B.Cu" "B.Mask")
+		(pinfunction "12V")
+		(pintype "input+no_connect")
+		(uuid "64558319-3b87-44be-8057-e75cad34cf21")
+	)
+	(pad "6" smd rect
+		(at -0.5 0.4206 180)
+		(size 1.5 13.6412)
+		(layers "F.Cu" "F.Mask")
+		(pinfunction "DO")
+		(pintype "input")
+		(uuid "716d87a9-4752-4c43-8aeb-01f3c13f2e85")
+	)
+	(pad "7" smd rect
+		(at 0.5 0.4206 180)
+		(size 1.5 13.6412)
+		(layers "B.Cu" "B.Mask")
+		(pinfunction "3V3")
+		(pintype "input")
+		(uuid "5cb34674-b690-4198-b249-3c15fd2bb685")
+	)
+	(pad "8" smd rect
+		(at 1.5 0.4206 180)
+		(size 1.5 13.6412)
+		(layers "F.Cu" "F.Mask")
+		(pinfunction "3V3")
+		(pintype "input")
+		(uuid "85c91145-35ba-489c-adcb-e7b52fdec5a5")
+	)
+	(pad "9" smd rect
+		(at 2.5 0.4206 180)
+		(size 1.5 13.6412)
+		(layers "B.Cu" "B.Mask")
+		(pinfunction "DI")
+		(pintype "input")
+		(uuid "1777659c-c4af-4ff2-ba96-b22c04ae7ed4")
+	)
+	(pad "10" smd rect
+		(at 3.5 0.4206 180)
+		(size 1.5 13.6412)
+		(layers "F.Cu" "F.Mask")
+		(pinfunction "CS")
+		(pintype "input")
+		(uuid "92543d61-f50b-414e-8279-9d0f04454364")
+	)
+	(pad "11" smd rect
+		(at 4.5 0.4206 180)
+		(size 1.5 13.6412)
+		(layers "B.Cu" "B.Mask")
+		(pinfunction "GND")
+		(pintype "input")
+		(uuid "bb75cdf0-85ed-448f-81fe-d8aee586b841")
+	)
+	(pad "12" smd rect
+		(at 5.5 0.4206 180)
+		(size 1.5 13.6412)
+		(layers "F.Cu" "F.Mask")
+		(pinfunction "GND")
+		(pintype "input")
+		(uuid "9eb6e23f-9a0f-4150-aafe-e36de21406d2")
+	)
+)

hardware/re-bba-rb/CPL_ROTATIONS.md

@@ -0,0 +1,121 @@
+# CPL rotation corrections — re-bba-rb
+
+`re-bba-rb-cpl.csv` is generated from `kicad-cli pcb export pos` (raw KiCad
+rotation values), **then hand-corrected** for the parts below before each
+regeneration. This file exists because that correction step is easy to lose
+silently — regenerating the CPL "the normal way" wipes it out, and there is
+no automated check that would catch that. Read this before touching the CPL.
+
+## Why this exists
+
+KiCad's per-footprint rotation is measured from an arbitrary reference baked
+into whoever drew that footprint — it does not reliably match what JLCPCB's
+placement machine expects. This is a well-known, generic problem (see
+`cpl_rotations_db.csv` from the JLCKicadTools / kicad-jlcpcb-tools projects
+for the community's attempt at a fix), but **the generic community
+correction table was tried on this board and found wrong** — it claims
+`LQFP-: 270°`, but on this exact board/toolchain pairing (KiCad 10 +
+`kicad-cli pcb export pos`, not the dedicated plugin) the raw LQFP/QFN
+rotation is already correct. The generic table's values are calibrated
+against that plugin's own raw-rotation baseline, which is not the same
+baseline `kicad-cli`'s raw CSV export produces (different Y-axis handling
+between the two tools). **Do not reapply the community table wholesale to
+this board.** Every correction below was derived per-part from direct visual
+verification against JLCPCB's placement-preview render, not from that table.
+
+## Rotation sign convention
+
+The CPL uses JLCPCB's Y-up coordinate frame (`kicad-cli`'s csv pos format
+already negates Y from KiCad's native Y-down). In that frame, **increasing
+rotation angle is counter-clockwise** (standard math convention). So when
+the user reports "needs N degrees clockwise", the correction applied is
+**`new = (old - N) % 360`**, not `+N`. Get this backwards and every fix
+lands 2×N off instead of correct.
+
+## How the correction was (re-)applied each time
+
+```python
+import csv
+corrections = { 'REF': degrees, ... }   # positive = CCW, negative = CW
+with open('re-bba-rb-cpl.csv', newline='') as f:
+    rows = list(csv.DictReader(f))
+for r in rows:
+    if r['Designator'] in corrections:
+        old = float(r['Rotation'])
+        new = (old + corrections[r['Designator']]) % 360
+        r['Rotation'] = f"{new:.6f}"
+with open('re-bba-rb-cpl.csv', 'w', newline='') as f:
+    writer = csv.DictWriter(f, fieldnames=['Designator','Mid X','Mid Y','Layer','Rotation'])
+    writer.writeheader()
+    writer.writerows(rows)
+```
+
+When regenerating the CPL from scratch (e.g. after a reroute or component
+move), **re-run `kicad-cli pcb export pos` for fresh positions, then
+reapply every correction below** — don't just diff/copy the old file, since
+positions can legitimately change while rotations still need the same
+correction offset applied on top.
+
+## Confirmed correct as-is — apply NO correction
+
+- **U8, U11 (LQFP-48/64)**, **U9 (QFN-48)** — "all large chips are right"
+  (user, direct placement-preview check). Raw KiCad rotation is correct.
+- **U4 (SOT-23-5)** — confirmed good *after* the -90° family correction
+  below was applied (net rotation 270°, i.e. raw 0° − 90°).
+- **J2 (HR911105A magjack, rot=90° in the PCB file)** — not a CPL-rotation
+  question (J2 doesn't need per-part correction below, it's not in the CPL
+  correction set), but its physical orientation was independently verified:
+  the RJ45 signal pins (pins 1–8, footprint local +Y) map to absolute −X
+  under the board's 90° placement rotation, which correctly faces the
+  board's tongue/cable-exit edge. Pin 1 appearing to "face outside the
+  board" in the placement render is *expected*, not a defect — the RJ45
+  contacts are always near the cable-insertion opening by construction.
+
+## Corrections applied (all currently in `re-bba-rb-cpl.csv`)
+
+Each row: designator, package, raw→corrected, confidence.
+
+| Ref | Package | Raw | Corrected | Confidence |
+|---|---|---|---|---|
+| U7  | SOIC-8 | 90°  | **180°** | Reconstructed hypothesis (see below) — not independently re-confirmed |
+| U10 | SOIC-8 | 0°   | **90°**  | Reconstructed hypothesis — not independently re-confirmed |
+| D1  | SOT-23-6 | 0°   | **270°** | Reconstructed hypothesis — not independently re-confirmed |
+| D4  | SOT-23-6 | 180° | **90°**  | Reconstructed hypothesis — not independently re-confirmed |
+| D5  | SOT-23-6 | 180° | **90°**  | Reconstructed hypothesis — not independently re-confirmed |
+| U12 | SOT-23-6 | 180° | **90°**  | Reconstructed hypothesis — not independently re-confirmed |
+| U1  | SOT-23-5 | 180° | **0°** (two corrections: -90° then another -90°, user-confirmed both times) | **Confirmed** by direct user feedback, twice |
+| Q1  | SOT-23 (bottom layer) | -90° | **90°** | **Confirmed** ("upside down" = 180°, direction-agnostic) |
+| Q2  | SOT-23 (bottom layer) | -90° | **90°** | **Confirmed** (same as Q1) |
+| D2  | custom `SON50P110X213X50-7` | 0°   | **270°** | **Confirmed** ("90° clockwise") |
+| D3  | `Diode_SMD:D_SMA` | 180° | **0°**   | **Confirmed** ("180°", direction-agnostic) |
+| C65 | `Capacitor_SMD:CP_Elec_6.3x7.7` | 0°   | **180°** | **Confirmed** ("180°", direction-agnostic) |
+| U2  | SOT-583-8 | 180° | **90°**  | **Confirmed** ("90° clockwise") |
+
+**"Reconstructed hypothesis" parts (U7, U10, D1, D4, D5, U12) explained:**
+the user reported "SOIC and SOT chips are rotated 90°, direction unsure."
+Cross-referencing against *earlier* feedback in the same session — where a
+-90° correction had been applied to the top-layer SOT-23 parts and NOT
+flagged as wrong, while the same -90° applied to a SOIC part (U10) WAS
+flagged wrong — implies SOT-23 needs -90° and SOIC needs the opposite,
++90°. This is indirect reasoning, not a fresh direct check, and **U1 later
+proved that even within one confirmed-wrong-by-90°-family, the correction
+does NOT reliably generalize per package type** (U1 and U4 are both
+SOT-23-5, both got the -90° family correction, but U1 needed a *second*
+-90° on top while U4 was already correct) — so treat every "reconstructed
+hypothesis" row above as **worth a fresh placement-preview check**, not
+settled fact, despite no contradicting feedback having come in since.
+
+## Parts never checked at all
+
+Every 0402/0603/0805 passive (R/C/L), J1/J3/J4 connectors, the custom
+`U3` footprint (`hardware:SOT95P280X110-6N`), and anything else not listed
+above is sitting at **raw, unverified KiCad rotation** in the CPL. Passives
+in symmetric packages are usually fine raw (this matched observed behavior
+for the ones implicitly checked), but this has not been confirmed
+part-by-part the way the table above was.
+
+## Bottom line for whoever picks this up next
+
+Before ordering assembly, re-check the *entire* board in JLCPCB's (or
+whatever assembler's) placement preview — this file only covers what's been
+individually verified so far, not a general guarantee the CPL is correct.

hardware/re-bba-rb/Power.kicad_sch

@@ -3433,7 +3433,7 @@
 				)
 			)
 		)
-		(property "MPN" "0402WGF1503TCE"
+		(property "MPN" "RC0402FR-07150KL"
 			(at 0 0 0)
 			(hide yes)
 			(show_name no)
@@ -3444,7 +3444,7 @@
 				)
 			)
 		)
-		(property "Manufacturer" "UNI-ROYAL"
+		(property "Manufacturer" "YAGEO"
 			(at 0 0 0)
 			(hide yes)
 			(show_name no)
@@ -3455,7 +3455,7 @@
 				)
 			)
 		)
-		(property "LCSC" "C25755"
+		(property "LCSC" "C93947"
 			(at 0 0 0)
 			(hide yes)
 			(show_name no)
@@ -3971,7 +3971,7 @@
 				)
 			)
 		)
-		(property "MPN" "19-217/GHC-YR1S2/3T"
+		(property "MPN" "KT-0603G"
 			(at 33.02 60.96 0)
 			(hide yes)
 			(show_name no)
@@ -3982,7 +3982,7 @@
 				)
 			)
 		)
-		(property "LCSC" "C72043"
+		(property "LCSC" "C12624"
 			(at 33.02 60.96 0)
 			(hide yes)
 			(show_name no)
@@ -3993,7 +3993,7 @@
 				)
 			)
 		)
-		(property "Manufacturer" "Everlight"
+		(property "Manufacturer" "Hubei KENTO"
 			(at 33.02 60.96 0)
 			(hide yes)
 			(show_name no)
@@ -5244,7 +5244,7 @@
 				)
 			)
 		)
-		(property "MPN" "19-217/GHC-YR1S2/3T"
+		(property "MPN" "KT-0603G"
 			(at 48.26 78.74 0)
 			(hide yes)
 			(show_name no)
@@ -5255,7 +5255,7 @@
 				)
 			)
 		)
-		(property "LCSC" "C72043"
+		(property "LCSC" "C12624"
 			(at 48.26 78.74 0)
 			(hide yes)
 			(show_name no)
@@ -5266,7 +5266,7 @@
 				)
 			)
 		)
-		(property "Manufacturer" "Everlight"
+		(property "Manufacturer" "Hubei KENTO"
 			(at 48.26 78.74 0)
 			(hide yes)
 			(show_name no)
@@ -5758,7 +5758,7 @@
 				(justify left)
 			)
 		)
-		(property "Value" "330"
+		(property "Value" "49.9"
 			(at 36.83 56.07 0)
 			(show_name no)
 			(do_not_autoplace no)
@@ -5802,7 +5802,7 @@
 				)
 			)
 		)
-		(property "MPN" "0402WGF3300TCE"
+		(property "MPN" "0402WGF4999TCE"
 			(at 36.83 52.07 0)
 			(hide yes)
 			(show_name no)
@@ -5813,7 +5813,7 @@
 				)
 			)
 		)
-		(property "LCSC" "C25104"
+		(property "LCSC" "C25120"
 			(at 36.83 52.07 0)
 			(hide yes)
 			(show_name no)
@@ -7123,7 +7123,7 @@
 				(justify left)
 			)
 		)
-		(property "Value" "330"
+		(property "Value" "49.9"
 			(at 52.07 76.39 0)
 			(show_name no)
 			(do_not_autoplace no)
@@ -7167,7 +7167,7 @@
 				)
 			)
 		)
-		(property "MPN" "0402WGF3300TCE"
+		(property "MPN" "0402WGF4999TCE"
 			(at 52.07 72.39 0)
 			(hide yes)
 			(show_name no)
@@ -7178,7 +7178,7 @@
 				)
 			)
 		)
-		(property "LCSC" "C25104"
+		(property "LCSC" "C25120"
 			(at 52.07 72.39 0)
 			(hide yes)
 			(show_name no)
@@ -7358,7 +7358,7 @@
 				)
 			)
 		)
-		(property "MPN" "0402WGF1002TCE"
+		(property "MPN" "RC0402FR-0710KL"
 			(at 0 0 0)
 			(hide yes)
 			(show_name no)
@@ -7369,7 +7369,7 @@
 				)
 			)
 		)
-		(property "Manufacturer" "UNI-ROYAL"
+		(property "Manufacturer" "YAGEO"
 			(at 0 0 0)
 			(hide yes)
 			(show_name no)
@@ -7380,7 +7380,7 @@
 				)
 			)
 		)
-		(property "LCSC" "C25744"
+		(property "LCSC" "C60490"
 			(at 0 0 0)
 			(hide yes)
 			(show_name no)
@@ -7560,7 +7560,7 @@
 				)
 			)
 		)
-		(property "MPN" "0402WGF1002TCE"
+		(property "MPN" "RC0402FR-0710KL"
 			(at 0 0 0)
 			(hide yes)
 			(show_name no)
@@ -7571,7 +7571,7 @@
 				)
 			)
 		)
-		(property "Manufacturer" "UNI-ROYAL"
+		(property "Manufacturer" "YAGEO"
 			(at 0 0 0)
 			(hide yes)
 			(show_name no)
@@ -7582,7 +7582,7 @@
 				)
 			)
 		)
-		(property "LCSC" "C25744"
+		(property "LCSC" "C60490"
 			(at 0 0 0)
 			(hide yes)
 			(show_name no)

hardware/re-bba-rb/TODO.md

@@ -6,6 +6,125 @@ manufacturing limits. Status 2026-07-18: **all three critical findings fixed
 in schematic AND PCB** (ERC 0, DRC 0 errors / 0 unconnected / 0 parity);
 remaining work is the Functional/Broader/ordering lists below.
 
+**Status 2026-07-22 (last-check pass):** ERC still clean (2 known-benign
+`lib_symbol_issues` on the generic Q_NPN_BEC/Q_PNP_BEC library symbols, not
+real problems). DRC: 0 unconnected items board-wide (incl. J3 — all 24 pads
+now carry real net copper, confirmed by direct pad/net inspection, not just
+the ratsnest count); 242 total violations, of which only **4 are errors**
+(2× `clearance` + 2× `hole_clearance`, two GND vias at (190.78/190.34, 58.58)
+0 mm from the `/Power/3V3` zone on In2.Cu — see Functional/robustness below),
+1 `track_dangling` (a 0.06 mm stub on `/exi/EXI_MOSI_RAW` near (188.39,
+57.52), likely harmless routing debris), and the rest are silkscreen
+warnings (171 overlap, 60 over-copper, 6 edge-clearance). This session also
+did extensive photo-based mechanical verification and a real J3 Y-position
+correction — see "Verify mechanical fit" below — and re-added fiducials with
+a different footprint/position than this file previously documented.
+
+**Status 2026-07-24 (major session):** ERC 0 (same 2 known-benign warnings +
+1 expected `power_pin_not_driven` on J5's `EXI_GND`, see below — not a real
+problem, that net has no power-symbol driver by design). DRC: 0 unconnected
+items, 280 total violations — same silkscreen-warning baseline as before
+plus `npth_inside_courtyard` (27, J5's mouse-bite holes sit close to J2's
+courtyard, judged benign — holes, not a component body) and 1 harmless
+`track_dangling`. The 2 GND-vias-vs-3V3-zone short from 2026-07-22 is
+**gone** (resolved somewhere in this session's PCB work, confirmed via fresh
+DRC). Gerbers/BOM/CPL all regenerated and verified current as of this pass.
+Major work this session:
+- **D6/D8/D9/D12 green LEDs swapped** Everlight 19-217/GHC-YR1S2/3T (C72043,
+  out of stock) → Hubei KENTO KT-0603G (C12624) — same 0603 footprint, same
+  manufacturer family as the already-used red KT-0603R (D7/D11). Series
+  resistors R37/R41/R42 changed 330 Ω → **49.9 Ω** (reused C25120, the same
+  part already on R26–R29 — no new BOM line) to compensate for KT-0603G's
+  higher Vf (3.1 V typ.) and restore comparable brightness (~4 mA vs the
+  ~0.6 mA the old resistor value would have given it). D12/D13 (RGB channels,
+  driven directly by the FPGA's `SB_RGBA_DRV` hard macro, no series resistor)
+  need no resistor change — flagged as slightly reduced current-source
+  headroom at the higher Vf, not fixed (nothing to fix, no resistor exists).
+  - [ ] **D13 (yellow, Everlight C72038) and the 10 kΩ 0402 resistor
+        (UNI-ROYAL C25744, used by 12 designators) are ALSO reported out of
+        stock** — real in-stock alternatives were being researched
+        (candidates: Hubei KENTO KT-0603Y/KT-0805Y for D13; YAGEO
+        RC0402FR-0710KL C60490 or Vishay CRCW040210K0FKED C71617 for the
+        10k) but never confirmed/committed — stock claims from web search
+        proved unreliable earlier this session (contradicted by direct
+        JLCPCB part-page checks twice), so these need a live stock check
+        before ordering, same as the green LED did.
+- **J5 added**: a second SP1 gold-finger connector, footprint copied from
+  the eth2sp1 open-source project (github.com/jochemvdmeulen/eth2sp1),
+  library file `hardware/SP1_eth2sp1_reference.kicad_mod`. Real purpose:
+  hand-solder insert for J3 — J5 is fabricated on this same board/panel via
+  a mouse-bite tab, snapped off after production, and soldered onto J3 so
+  its gold fingers protrude past the board edge into the GC slot (J3 itself
+  uses thru-hole insert pads, not bare gold fingers). Pad length tuned to
+  13.5 mm + board thickness (1.1412 mm) = 14.6412 mm, then trimmed −1.0 mm to
+  **13.6412 mm** (near/board-edge-side pad edge held fixed 0.6 mm off the
+  nose throughout, matching eth2sp1's original tip clearance). J5 pins
+  1,3–10 stay no-connect (DNP, no live signals); pins 2/11/12 (shield/ground)
+  tie to a new **`EXI_GND`** net — a dedicated reference-plane net for the
+  fingers, deliberately kept separate from board `GND` until physically
+  joined to J3 by solder (J5 is a separate PCB fragment until then).
+  - [x] Mouse-bite tab: 27× 0.4 mm NPTH holes at X=106.8900, spanning the
+        full Y=48.1–66.6 tongue height (both endpoints landing on the
+        original tongue corners as half-moon scallops) — footprint
+        `MouseBites_J5`. **Has disappeared from the PCB and needed
+        re-adding twice this session** (cause unknown — likely an
+        accidental GUI selection/delete, watch for a third time).
+  - [ ] **User is routing the `EXI_GND` reference plane + stitching vias
+        under J5's fingers** — in progress, not finished. Guidance given:
+        multiple vias per ground pad (not just one via per pin), plus
+        stitching vias flanking the *signal* fingers (CLK/MOSI/MISO/CS)
+        too, not just the 3 named ground pins — that's what actually
+        controls impedance at the trace-to-finger transition.
+  - [ ] J2's `HANRUN_HR911105A.kicad_mod` footprint has a cosmetic-only
+        defect: pads 15/16 (2.445 mm ground/shield tabs) stick out ~0.97 mm
+        past the F.Fab body-outline rectangle (top and bottom, symmetric).
+        **Confirmed NOT a DRC/manufacturability issue** — the real courtyard
+        (F.CrtYd) properly encloses both pads with ~0.28 mm margin; this is
+        why JLCPCB's placement-preview render looked alarming (it draws the
+        undersized F.Fab rectangle as the "body"). Offered to fix the F.Fab
+        rectangle for cosmetic accuracy; not done.
+- **Gateware pin constraints — DONE** (was the "Write the re-bba-rb pin
+  constraints" item below, now resolved): `exi_bba/synth.py`'s
+  `IceBreakerPlatform` no longer targets the iCEbreaker — every pin pulled
+  directly from the schematic netlist and verified placed by nextpnr.
+  Also fixed two real bugs found in the process: **LED polarity was
+  backwards** (D6/D7 are active-high on this board, opposite the
+  iCEbreaker's onboard active-low LEDs the old code assumed) and **removed
+  a reference to a physical button that doesn't exist on this board** (the
+  iCEbreaker's `BTN_N` was dev-board-only; `panel_btn` now ties idle).
+  - [x] **Real hardware conflict found and fixed**: the schematic originally
+        put `ETH_INT` on U9 pin 35, which **physically conflicts with the
+        iCE40UP5K's PLL hard macro** — pin 35 cannot be used as an *input*
+        while the PLL is instantiated (confirmed both by nextpnr's own chip
+        database and by direct testing: an unrelated input signal swapped
+        onto pin 35 reproduces the identical conflict; an *output* signal
+        on pin 35 works fine — the restriction is input-direction-specific,
+        not a blanket "pin 35 is unusable"). Board was still in design, so
+        fixed at the source: **`ETH_INT` moved from U9 pin 35 to pin 13**
+        (schematic + PCB both reworked and verified — pin 13 was confirmed
+        via icestorm's own pin database to be the *only* spare GPIO on this
+        exact SG48 package/board combo; all other 38 usable pins were
+        already assigned). PCB reroute done and DRC-clean (0 unconnected,
+        0 shorts). An alternative (wr_n 36→35, rd_n 37→36, int_n→37, keeping
+        ETH_INT physically clustered with the rest of the ethernet bus) was
+        evaluated and rejected — it works but only found 1 passing seed out
+        of 5 tried, with much thinner timing margin (0.4% vs 3%) than the
+        pin-13 arrangement.
+  - [x] **Timing verified — closes, seed-sensitive**: seed 1 narrowly missed
+        (`capture_clk` 53.08 MHz vs 54.02 MHz target), seed 3 passes both
+        domains cleanly (`clk` 37.82 MHz vs 24 MHz, `capture_clk` 55.69 MHz
+        vs 54.02 MHz) — consistent with this design's known seed-sensitivity
+        (routing-dominated at ~22% LC utilization). `build/top.bin` on disk
+        is the seed-3 result. Re-verified after the PCB reroute — identical
+        numbers, as expected (PCB copper doesn't affect FPGA-internal
+        timing).
+  - [ ] **Known bug, not fixed**: `synth.py`'s built-in `--seeds N` sweep
+        loop throws silent exceptions on seeds after the first when run in
+        one process (pre-existing, unrelated to this session's pin changes)
+        — worked around by invoking each seed as a separate process. The
+        convenience one-command multi-seed workflow needs debugging if
+        wanted again.
+
 ## Critical — ALL RESOLVED (schematic + PCB, verified 2026-07-18)
 
 - [x] **EXI DO/DI swapped at J3 — FIXED 2026-07-17** (all copper unchanged).
@@ -72,19 +191,21 @@ remaining work is the Functional/Broader/ordering lists below.
 
 ## Functional / robustness
 
-- [ ] **iceprog pin mismatch — schematic FIXED 2026-07-18**: FLASH_CS moved
-      ADBUS3→ADBUS4 (U8 pin 21), CDONE ACBUS1→ADBUS6 (pin 23), CRESET
-      ACBUS0→ADBUS7 (pin 24) — now exactly stock iceprog / iCEbreaker
+- [x] **iceprog pin mismatch — schematic FIXED 2026-07-18, PCB rerouted**:
+      FLASH_CS moved ADBUS3→ADBUS4 (U8 pin 21), CDONE ACBUS1→ADBUS6 (pin 23),
+      CRESET ACBUS0→ADBUS7 (pin 24) — now exactly stock iceprog / iCEbreaker
       channel-A convention; old pins are NC. Pull-ups R11/R12 unchanged.
-      - [ ] PCB: reroute the three lines to the new U8 pins (F8 shows the
-            pad-net changes).
+      Verified 2026-07-22: 0 DRC violations in the U8 pin area, 0 unconnected
+      items board-wide.
 - [x] **TPS2116 PR1 divider margin — FIXED 2026-07-18**: R3 200k→150k
       (0402WGF1503TCE, LCSC C25755). PR1 = 1.32 V nominal; switchover at
       GC_3V3 = 2.30–2.70 V worst-case — safely below the 3.3 V rail. (Value
       change only, same footprint — no PCB work.)
-- [ ] **ETH_RST pull-up — schematic FIXED 2026-07-18**: R36 10 k (C25744)
-      from ETH_RST to **ETH_3V3** (low when ETH rail off).
-      - [ ] PCB: place/route R36 near U11 pin 48.
+- [x] **ETH_RST pull-up — schematic FIXED 2026-07-18, PCB placed/routed**:
+      R36 10 k (C25744) from ETH_RST to **ETH_3V3** (low when ETH rail off),
+      at (148.49, 61.7225) near U11 pin 48. Verified 2026-07-22: nets
+      `/ethernet/ETH_RST` + `/ethernet/ETH_3V3` both present on the footprint,
+      0 unconnected items.
 - [ ] **Gateware: gate all outputs on GC_ON** — when GC_ON=0 the W5100S is
       unpowered (U12) and the GC is off, but FPGA banks stay at 3.3 V. Hold
       the W5100S bus and EXI outputs Hi-Z/low to avoid back-powering.
@@ -93,41 +214,88 @@ remaining work is the Functional/Broader/ordering lists below.
       board PCF.
 - [ ] **Gateware: EXI INT drive style** — prefer open-drain emulation (drive
       low / release) on J3.3 rather than push-pull high.
+- [ ] **New 2026-07-22: 2 GND vias short the `/Power/3V3` zone on In2.Cu** —
+      found during the last DRC pass, 4 error-severity violations (2×
+      `clearance` + 2× `hole_clearance`, both 0 mm actual). Two GND vias at
+      (190.78, 58.58) and (190.34, 58.58) — just south of J3's courtyard,
+      likely stitching vias added during the J3 reroute — sit directly on
+      top of the 3V3 pour on In2.Cu. This is a real short risk, not a
+      manufacturability nit: move or delete these two vias (or void the 3V3
+      zone locally) before ordering. Also 1 harmless `track_dangling`: a
+      0.06 mm stub on `/exi/EXI_MOSI_RAW` near (188.39, 57.52) — routing
+      debris, delete when convenient.
 
 ## Broader items (beyond the wiring review — block fab on the first two)
 
-- [ ] **Write the re-bba-rb pin constraints** — `exi_bba/synth.py` still targets
-      the iCEbreaker. Full board pin map: EXI_MOSI = 4 (IOB_8a, in),
-      EXI_MISO = 3 (IOB_9b, out), EXI_CLK = 44 (G6), EXI_CS = 45,
-      EXI_INT = 46; W5100S bus on the IOT bank (23–43); CLK12 = 20 (G3);
-      GC_ON = 21; ETH_RST = 2; UART: FPGA RX = 18 (net UART_TXD!, FTDI
-      output), FPGA TX = 19; **debug: LED_G = 47 (heartbeat), LED_R = 48
-      (EXI activity), DBG0–4 = 9/10/11/12/6 (J4 header)**. Pure software;
-      do before ordering to prove the pinout.
+- [x] **Write the re-bba-rb pin constraints — DONE 2026-07-24**, see the
+      "Status 2026-07-24" note at the top for full details. Real board pin
+      map: EXI_MOSI = 4 (IOB_8a, in), EXI_MISO = 3 (IOB_9b, out),
+      EXI_CLK = 44 (G6), EXI_CS = 45, EXI_INT = 46; W5100S bus A0=42 A1=38
+      D0-D7=34/32/31/28/27/26/25/23 CS_N=43 RD_N=37 WR_N=36 RST_N=2;
+      **ETH_INT moved from the schematic's original pin 35 to pin 13** (pin
+      35 physically conflicts with the PLL for input use — hardware
+      constraint, not fixable in software, resolved via schematic+PCB
+      rework since the board was still in design); CLK12 = 20 (G3);
+      UART: FPGA RX = 18 (net UART_TXD!, FTDI output), FPGA TX = 19;
+      debug: LED_G = 47 (heartbeat, active-high), LED_R = 48 (EXI activity,
+      active-high), DBG0–4 = 9/10/11/12/6 (J4 header). No physical button
+      on this board — the old iCEbreaker BTN_N reference was removed.
+      Placement + timing verified (nextpnr, seed 3: clk 37.82 MHz/24 target,
+      capture_clk 55.69 MHz/54.02 target, both PASS).
 - [ ] **Debug provisions — schematic DONE 2026-07-18** (was: board had none):
-      - D6 green heartbeat LED (Everlight 19-217/GHC-YR1S2/3T, C72043,
-        Basic) on FPGA pin 47 (LED_G) via R37 330 Ω (C25104);
+      - D6 green heartbeat LED (**Hubei KENTO KT-0603G, C12624** — swapped
+        2026-07-24, Everlight original was out of stock) on FPGA pin 47
+        (LED_G) via R37 **49.9 Ω** (C25120, swapped from 330 Ω same day to
+        compensate for KT-0603G's higher Vf — see the 2026-07-24 status note);
       - D7 red EXI-activity LED (KENTO KT-0603R, C2286, Basic) on pin 48
-        (LED_R) via R38;
+        (LED_R) via R38 (unchanged, this one was never out of stock);
       - J4 6-pin debug header (unpopulated, in_bom no): GND + DBG0–4 =
         FPGA pins 9/10/11/12/6 — route EXI CLK/CS/MOSI/MISO copies here in
         gateware for logic-analyzer bring-up;
       - TP1 3V3, TP2 1V2, TP3 ETH_3V3 (ethernet sheet), TP4 GC_ON, TP5 GND
         (1.5 mm pads, in_bom no);
-      - FID1–3 fiducials placed directly on the PCB (board-only) at
-        (195, 68.5)/(131, 48)/(163, 44.5) — copper-clear, DRC 0.
-      - [ ] PCB: place/route the 11 schematic footprints (D6/D7, R36/R37/
-            R38, TP1–5, J4) — F8 pulls them in. LEDs need visibility with
-            the GC shell on: place near the RJ45/USB edge if possible.
-- [ ] **Verify mechanical fit** (bench item — cannot be verified in repo):
-      outline vs the SP1 slot, RJ45/USB-C protrusion vs the GC serial port
-      bay opening. An earlier commit says "need to remeasure PCB outline".
-      Note 2026-07-18: the J3 footprint (12 contacts, 1 mm effective pitch,
-      two staggered depth rows, front-side only, fingers to the board edge
-      per the .kicad_dru exception) is the geometry derived from the
-      physical sp1_test_plug iterations — the test-plug project itself
-      contains no reusable finger footprint to diff against, so the
-      provenance is the physical test, not a file comparison.
+      - FID1–3 fiducials: **superseded 2026-07-22**, see the fiducials entry
+        under "JLCPCB ordering notes" below for current footprint/positions.
+      - [x] **PCB: place/route the 11 schematic footprints — DONE**, verified
+            2026-07-22: D6/D7/R37/R38/TP1–5/J4 all present with correct net
+            assignments (`Net-(D6-A)`/`Net-(D7-A)`/`/fpga/LED_G`/`/fpga/LED_R`
+            for the LEDs, `/Power/3V3`/`/fpga/1V2`/`/ethernet/ETH_3V3`/
+            `/GC_ON`/`GND` for TP1–5, `/fpga/DBG0-4`+`GND` for J4), 0
+            unconnected items. LED visibility vs the GC shell not
+            re-verified here (bench item).
+- [x] **Verify mechanical fit — major progress 2026-07-22** (bench item,
+      photo-based, this session): the user measured the real GameCube SP1
+      bay using an Android reference-square app (ImageMeter) against a 2 cm
+      calibration square, photographing up into the bay with J2 (Ethernet
+      jack) as the fixed anchor. Cross-referencing those measurements against
+      the PCB's J3/J2 courtyards (courtyard, not pad or slot, is the correct
+      mechanical reference) found J3 was mispositioned in Y by ~5 mm.
+      Orientation (which real-world edge maps to which PCB edge) was
+      independently confirmed via a numerical fit check (original pairing:
+      ~2–3 mm residual both sides; a candidate 180°-about-X-axis reflection
+      was tested and rejected: 6.3 mm residual on one side) plus a rendered
+      PCB PDF sanity check.
+      - [x] **J3 shifted**: `(at 189.85 59.9)` → `(at 189.85 54.9)`, i.e.
+            **Y −5.0 mm**, X unchanged (X was checked against both bay edges
+            using the board's true front/back edges — no shift needed). J3
+            was fully unrouted at shift time (0 track segments touched any
+            of its 24 pads, verified beforehand) so the move was electrically
+            free; the resulting 183 DRC collisions (D2 + EXI_* net clearances
+            in the new J3 footprint area) have since been resolved by
+            rerouting — 0 J3-area DRC errors remain as of 2026-07-22, and J3
+            is now fully routed (see above).
+      - [ ] X/Y still not verified against real hardware — this was a
+            photo/measurement-based correction, not a fit-check against an
+            actual GameCube. Confirm on the bench when a unit is available.
+      - [ ] Insertion depth (Z, connector engagement into the slot) —
+            explicitly deferred by the user, not addressed this pass.
+      - Note 2026-07-18 (unchanged): the J3 footprint (12 contacts, 1 mm
+            effective pitch, two staggered depth rows, front-side only,
+            fingers to the board edge per the .kicad_dru exception) is the
+            geometry derived from the physical sp1_test_plug iterations —
+            the test-plug project itself contains no reusable finger
+            footprint to diff against, so the provenance is the physical
+            test, not a file comparison.
 - [x] **SP1 12 V rail viability — VERIFIED against existing projects
       (2026-07-17).** webhdx's IDE-EXI v2 for Serial Port 1 (which became the
       commercial M.2 Loader): "New switching power regulator supplies 3.3V@2A
@@ -197,10 +365,12 @@ remaining work is the Functional/Broader/ordering lists below.
       pin-compatible, but treat as a bring-up suspect if EXI ESD behaviour
       looks odd. C65 is an SMD electrolytic (Lelon VZH101M1ETR-0607, 25 V) —
       assembly-friendly, not THT as first assumed.
-- [ ] Fiducials: VERIFIED ABSENT (0 on the board, 2026-07-18). JLCPCB can
-      panel-add their own, but 3 board fiducials (1 mm copper dot, 2 mm mask
-      opening, asymmetric corners) is the robust choice — add with the debug
-      LEDs/test points pass.
+- [x] Fiducials: **placed 2026-07-22** — `Fiducial_0.5mm_Mask1mm` (0.5 mm
+      copper dot, 1 mm mask opening; downsized from the originally-planned
+      1 mm/2 mm footprint because no spot on the real board had >5 mm
+      clearance from other parts) at FID1 (160.0, 50.5), FID2 (184.2, 61.0),
+      FID3 (187.3, 47.5) — asymmetric placement, all verified genuinely
+      on-board against the true (non-bounding-box) board polygon, DRC 0.
 
 ## Housekeeping (repo) — done 2026-07-17
 

hardware/re-bba-rb/Usb Connector.kicad_sch

@@ -11798,7 +11798,7 @@
 				)
 			)
 		)
-		(property "MPN" "0402WGF1002TCE"
+		(property "MPN" "RC0402FR-0710KL"
 			(at -77.47 -77.47 0)
 			(hide yes)
 			(show_name no)
@@ -11809,7 +11809,7 @@
 				)
 			)
 		)
-		(property "Manufacturer" "UNI-ROYAL"
+		(property "Manufacturer" "YAGEO"
 			(at -77.47 -77.47 0)
 			(hide yes)
 			(show_name no)
@@ -11820,7 +11820,7 @@
 				)
 			)
 		)
-		(property "LCSC" "C25744"
+		(property "LCSC" "C60490"
 			(at -77.47 -77.47 0)
 			(hide yes)
 			(show_name no)

hardware/re-bba-rb/ethernet.kicad_sch

@@ -9415,7 +9415,7 @@
 				)
 			)
 		)
-		(property "MPN" "0402WGF1002TCE"
+		(property "MPN" "RC0402FR-0710KL"
 			(at 0 0 0)
 			(hide yes)
 			(show_name no)
@@ -9426,7 +9426,7 @@
 				)
 			)
 		)
-		(property "Manufacturer" "UNI-ROYAL"
+		(property "Manufacturer" "YAGEO"
 			(at 0 0 0)
 			(hide yes)
 			(show_name no)
@@ -9437,7 +9437,7 @@
 				)
 			)
 		)
-		(property "LCSC" "C25744"
+		(property "LCSC" "C60490"
 			(at 0 0 0)
 			(hide yes)
 			(show_name no)

hardware/re-bba-rb/exi.kicad_sch

@@ -1239,10 +1239,46 @@
 			(embedded_fonts no)
 		)
 	)
+	(no_connect
+		(at 110.49 90.17)
+		(uuid "01aed343-ee55-43ca-9d12-da07db63d213")
+	)
+	(no_connect
+		(at 110.49 85.09)
+		(uuid "2e2bbfb5-a908-4239-8dea-edf46f2663e7")
+	)
+	(no_connect
+		(at 110.49 95.25)
+		(uuid "368adb60-1f1b-4962-9592-468333e9a431")
+	)
+	(no_connect
+		(at 110.49 97.79)
+		(uuid "40142202-21fa-4f5a-a288-f2919aa8a958")
+	)
+	(no_connect
+		(at 110.49 77.47)
+		(uuid "474ac82a-129d-48a0-999c-ba722f9c922d")
+	)
+	(no_connect
+		(at 110.49 87.63)
+		(uuid "4adfedad-c278-4598-814f-b739c90ab29f")
+	)
 	(no_connect
 		(at 74.93 93.98)
 		(uuid "b855de1b-54c4-47f5-a83c-8776d2aea575")
 	)
+	(no_connect
+		(at 110.49 92.71)
+		(uuid "bdb944a3-7209-41cd-a72e-20674055f3d3")
+	)
+	(no_connect
+		(at 110.49 82.55)
+		(uuid "cd245ba5-932c-42ce-967b-527cd3fbace9")
+	)
+	(no_connect
+		(at 110.49 100.33)
+		(uuid "f6478aab-b777-458a-8a20-38b2badd0941")
+	)
 	(wire
 		(pts
 			(xy 64.77 96.52) (xy 62.23 96.52)
@@ -1255,7 +1291,7 @@
 	)
 	(wire
 		(pts
-			(xy 96.52 76.2) (xy 96.52 82.55)
+			(xy 24.13 81.28) (xy 24.13 87.63)
 		)
 		(stroke
 			(width 0)
@@ -1285,7 +1321,7 @@
 	)
 	(wire
 		(pts
-			(xy 96.52 90.17) (xy 96.52 95.25)
+			(xy 24.13 95.25) (xy 24.13 100.33)
 		)
 		(stroke
 			(width 0)
@@ -1383,6 +1419,16 @@
 		)
 		(uuid "a9b98f12-4996-44d1-ae46-2792ac2046f7")
 	)
+	(wire
+		(pts
+			(xy 38.1 95.25) (xy 38.1 100.33)
+		)
+		(stroke
+			(width 0)
+			(type default)
+		)
+		(uuid "aac1f9b8-1a7f-432f-a761-de465b824eee")
+	)
 	(wire
 		(pts
 			(xy 74.93 93.98) (xy 62.23 93.98)
@@ -1393,6 +1439,16 @@
 		)
 		(uuid "ac10f016-ef9e-402a-8ae0-3b78bd758afa")
 	)
+	(wire
+		(pts
+			(xy 38.1 81.28) (xy 38.1 87.63)
+		)
+		(stroke
+			(width 0)
+			(type default)
+		)
+		(uuid "bdb465b5-698e-4fe3-95e6-abb757bdacf8")
+	)
 	(wire
 		(pts
 			(xy 74.93 81.28) (xy 62.23 81.28)
@@ -1424,7 +1480,7 @@
 		(uuid "fd73b349-d700-4bfa-9b20-b662f3b5fa69")
 	)
 	(label "EXI_MOSI_RAW"
-		(at 27.94 90.17 180)
+		(at 58.42 41.91 180)
 		(effects
 			(font
 				(size 1.27 1.27)
@@ -1434,7 +1490,7 @@
 		(uuid "1673f89a-b196-4e3a-8b31-50ae5115685e")
 	)
 	(label "EXI_MISO_RAW"
-		(at 27.94 85.09 180)
+		(at 58.42 36.83 180)
 		(effects
 			(font
 				(size 1.27 1.27)
@@ -1453,8 +1509,18 @@
 		)
 		(uuid "2f6a1b3c-2b9e-4f1b-9d6a-6e8f4b0c1a2d")
 	)
+	(label "EXI_GND"
+		(at 110.49 102.87 0)
+		(effects
+			(font
+				(size 1.27 1.27)
+			)
+			(justify left)
+		)
+		(uuid "3847a147-ee7d-469e-b10b-cde365952105")
+	)
 	(label "EXI_INT"
-		(at 27.94 97.79 180)
+		(at 58.42 49.53 180)
 		(effects
 			(font
 				(size 1.27 1.27)
@@ -1474,7 +1540,7 @@
 		(uuid "5b8c3d1e-6f7a-4b9c-9d0e-1f2a3b4c5d6e")
 	)
 	(label "EXI_CS"
-		(at 27.94 87.63 180)
+		(at 58.42 39.37 180)
 		(effects
 			(font
 				(size 1.27 1.27)
@@ -1514,17 +1580,17 @@
 		(uuid "9e1d4a2b-8c3f-4a5e-b1d6-2f7c9e0a4b3d")
 	)
 	(label "12V_EXI"
-		(at 46.99 86.36 180)
+		(at 38.1 81.28 90)
 		(effects
 			(font
 				(size 1.27 1.27)
 			)
-			(justify right bottom)
+			(justify left bottom)
 		)
 		(uuid "a5f89a25-304f-4bd7-ad04-bee13500abd8")
 	)
 	(label "EXTIN_RAW"
-		(at 27.94 95.25 180)
+		(at 58.42 46.99 180)
 		(effects
 			(font
 				(size 1.27 1.27)
@@ -1543,8 +1609,18 @@
 		)
 		(uuid "c9d70ab0-2af1-490e-becd-c3978fe3fe26")
 	)
+	(label "EXI_GND"
+		(at 110.49 80.01 0)
+		(effects
+			(font
+				(size 1.27 1.27)
+			)
+			(justify left)
+		)
+		(uuid "d5e4c212-9d51-4b55-aa22-2e4e349b029c")
+	)
 	(label "EXI_CLK_RAW"
-		(at 27.94 92.71 180)
+		(at 58.42 44.45 180)
 		(effects
 			(font
 				(size 1.27 1.27)
@@ -1553,9 +1629,19 @@
 		)
 		(uuid "db4a6fbe-2eeb-435c-a6e4-0d2a028a1373")
 	)
+	(label "EXI_GND"
+		(at 110.49 105.41 0)
+		(effects
+			(font
+				(size 1.27 1.27)
+			)
+			(justify left)
+		)
+		(uuid "efd00d77-7e87-45bb-8c02-f9c931994a36")
+	)
 	(hierarchical_label "12V_EXI"
 		(shape output)
-		(at 96.52 76.2 90)
+		(at 24.13 81.28 90)
 		(effects
 			(font
 				(size 1.27 1.27)
@@ -1707,7 +1793,7 @@
 	)
 	(symbol
 		(lib_id "Device:C_Polarized")
-		(at 96.52 86.36 0)
+		(at 24.13 91.44 0)
 		(unit 1)
 		(body_style 1)
 		(exclude_from_sim no)
@@ -1717,7 +1803,7 @@
 		(dnp no)
 		(uuid "11c5a587-7b43-454b-8483-cecc6ffb0da5")
 		(property "Reference" "C65"
-			(at 99.06 85.09 0)
+			(at 26.67 90.17 0)
 			(show_name no)
 			(do_not_autoplace no)
 			(effects
@@ -1728,7 +1814,7 @@
 			)
 		)
 		(property "Value" "100uF"
-			(at 99.06 87.63 0)
+			(at 26.67 92.71 0)
 			(show_name no)
 			(do_not_autoplace no)
 			(effects
@@ -1739,7 +1825,7 @@
 			)
 		)
 		(property "Footprint" "Capacitor_SMD:CP_Elec_6.3x7.7"
-			(at 96.52 86.36 0)
+			(at 24.13 91.44 0)
 			(hide yes)
 			(show_name no)
 			(do_not_autoplace no)
@@ -1750,7 +1836,7 @@
 			)
 		)
 		(property "Datasheet" ""
-			(at 96.52 86.36 0)
+			(at 24.13 91.44 0)
 			(show_name no)
 			(do_not_autoplace no)
 			(effects
@@ -1760,7 +1846,7 @@
 			)
 		)
 		(property "Description" "Polarized capacitor"
-			(at 96.52 86.36 0)
+			(at 24.13 91.44 0)
 			(hide yes)
 			(show_name no)
 			(do_not_autoplace no)
@@ -1771,7 +1857,7 @@
 			)
 		)
 		(property "MPN" "VZH101M1ETR-0607"
-			(at 0 0 0)
+			(at -72.39 5.08 0)
 			(hide yes)
 			(show_name no)
 			(do_not_autoplace no)
@@ -1782,7 +1868,7 @@
 			)
 		)
 		(property "Manufacturer" "Lelon"
-			(at 0 0 0)
+			(at -72.39 5.08 0)
 			(hide yes)
 			(show_name no)
 			(do_not_autoplace no)
@@ -1793,7 +1879,7 @@
 			)
 		)
 		(property "LCSC" "C311617"
-			(at 0 0 0)
+			(at -72.39 5.08 0)
 			(hide yes)
 			(show_name no)
 			(do_not_autoplace no)
@@ -1804,7 +1890,7 @@
 			)
 		)
 		(property "Type" "Aluminum"
-			(at 96.52 86.36 0)
+			(at 24.13 91.44 0)
 			(hide yes)
 			(show_name no)
 			(do_not_autoplace no)
@@ -1815,7 +1901,7 @@
 			)
 		)
 		(property "V" "25V"
-			(at 96.52 86.36 0)
+			(at 24.13 91.44 0)
 			(hide yes)
 			(show_name no)
 			(do_not_autoplace no)
@@ -1842,7 +1928,7 @@
 	)
 	(symbol
 		(lib_id "PUSB3AB6Z_ES:PUSB3AB6Z_ES")
-		(at 38.1 91.44 0)
+		(at 68.58 43.18 0)
 		(unit 1)
 		(body_style 1)
 		(exclude_from_sim no)
@@ -1852,7 +1938,7 @@
 		(dnp no)
 		(uuid "165499df-6aee-4ac7-8721-5c64a577f026")
 		(property "Reference" "D2"
-			(at 27.94 79.6698 0)
+			(at 58.42 31.4098 0)
 			(show_name no)
 			(do_not_autoplace no)
 			(effects
@@ -1863,7 +1949,7 @@
 			)
 		)
 		(property "Value" "PUSB3AB6Z(ES)"
-			(at 27.94 101.6 0)
+			(at 58.42 53.34 0)
 			(show_name no)
 			(do_not_autoplace no)
 			(effects
@@ -1874,7 +1960,7 @@
 			)
 		)
 		(property "Footprint" "hardware:SON50P110X213X50-7"
-			(at 38.1 91.44 0)
+			(at 68.58 43.18 0)
 			(hide yes)
 			(show_name no)
 			(do_not_autoplace no)
@@ -1885,7 +1971,7 @@
 			)
 		)
 		(property "Datasheet" "https://assets.nexperia.com/documents/data-sheet/PUSB3AB6.pdf"
-			(at 38.1 91.44 0)
+			(at 68.58 43.18 0)
 			(hide yes)
 			(show_name no)
 			(do_not_autoplace no)
@@ -1896,7 +1982,7 @@
 			)
 		)
 		(property "Description" "6-channel 3.3V 0.15pF ultra-low-cap TVS array on EXI_CLK/CS/MOSI/MISO/INT + ExtIn, all channels used; tapped upstream of series resistors on the connector side"
-			(at 38.1 91.44 0)
+			(at 68.58 43.18 0)
 			(hide yes)
 			(show_name no)
 			(do_not_autoplace no)
@@ -1907,7 +1993,7 @@
 			)
 		)
 		(property "MPN" "PUSB3AB6Z(ES)"
-			(at 38.1 91.44 0)
+			(at 68.58 43.18 0)
 			(hide yes)
 			(show_name no)
 			(do_not_autoplace no)
@@ -1918,7 +2004,7 @@
 			)
 		)
 		(property "Manufacturer" "ElecSuper (2nd source of Nexperia PUSB3AB6Z)"
-			(at 38.1 91.44 0)
+			(at 68.58 43.18 0)
 			(hide yes)
 			(show_name no)
 			(do_not_autoplace no)
@@ -1929,7 +2015,7 @@
 			)
 		)
 		(property "LCSC" "C49383400"
-			(at 38.1 91.44 0)
+			(at 68.58 43.18 0)
 			(hide yes)
 			(show_name no)
 			(do_not_autoplace no)
@@ -2044,6 +2130,117 @@
 			)
 		)
 	)
+	(symbol
+		(lib_id "GameCube:Sp1_Connector")
+		(at 109.22 90.17 0)
+		(unit 1)
+		(body_style 1)
+		(exclude_from_sim no)
+		(in_bom no)
+		(on_board yes)
+		(in_pos_files yes)
+		(dnp yes)
+		(uuid "20452aa5-87af-4da4-8d33-0ef66ad5d3a1")
+		(property "Reference" "J5"
+			(at 97.79 73.406 0)
+			(show_name no)
+			(do_not_autoplace no)
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+				(justify left)
+			)
+		)
+		(property "Value" "SP1_REFERENCE_DNP"
+			(at 96.52 75.692 0)
+			(show_name no)
+			(do_not_autoplace no)
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+				(justify left)
+			)
+		)
+		(property "Footprint" "hardware:SP1_eth2sp1_reference"
+			(at 110.49 74.93 0)
+			(hide yes)
+			(show_name no)
+			(do_not_autoplace no)
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+			)
+		)
+		(property "Datasheet" ""
+			(at 110.49 74.93 0)
+			(hide yes)
+			(show_name no)
+			(do_not_autoplace no)
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+			)
+		)
+		(property "Description" "SP1 gold-finger insert, copied from eth2sp1 (github.com/jochemvdmeulen/eth2sp1). Fabricated on this panel via mouse-bite tab, snapped off and hand-soldered onto J3. Signal/power pins (1,3-10) are no-connect (mechanical/electrical bring-up happens after hand-soldering); pins 2,11,12 (shield/ground) tie to EXI_GND, a dedicated reference-plane net for the fingers, kept separate from board GND until joined to J3 by solder. Always DNP (bare PCB copper, not a purchasable part)."
+			(at 110.49 74.93 0)
+			(hide yes)
+			(show_name no)
+			(do_not_autoplace no)
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+			)
+		)
+		(pin "1"
+			(uuid "59f0562f-32cd-4c7e-8927-a6c6a05f76fc")
+		)
+		(pin "2"
+			(uuid "5b7a0a5d-c019-4f77-9e52-64adf18b75a2")
+		)
+		(pin "3"
+			(uuid "2cda2185-1344-41ae-9d93-6deff5ea9bcc")
+		)
+		(pin "4"
+			(uuid "142fdbd2-0221-454e-8c59-95a54d5aac6c")
+		)
+		(pin "5"
+			(uuid "7fea9a74-d917-4b9e-9dcf-54493e2b2768")
+		)
+		(pin "6"
+			(uuid "938d1a3f-b581-4bd2-86b8-5d5a8c794fe2")
+		)
+		(pin "7"
+			(uuid "c9c4eee6-76ac-45d9-827e-309a8b734e92")
+		)
+		(pin "8"
+			(uuid "0a0570c4-6206-4ea6-93dd-18503b43a38f")
+		)
+		(pin "9"
+			(uuid "53b291ab-eac4-4987-94c1-3254b4199fed")
+		)
+		(pin "10"
+			(uuid "3652d701-3638-4a18-8bdb-a84a8e6057fb")
+		)
+		(pin "11"
+			(uuid "837a1ed3-35bf-4afc-a586-b44fd1ee0205")
+		)
+		(pin "12"
+			(uuid "9e906f82-5998-4a2c-924d-47cc63fc4ad0")
+		)
+		(instances
+			(project "re-bba-rb"
+				(path "/dbb182a6-d579-468e-b98b-6f0950da9e3a/1b071f68-b4ea-469c-942f-de06380c9077"
+					(reference "J5")
+					(unit 1)
+				)
+			)
+		)
+	)
 	(symbol
 		(lib_id "Device:R")
 		(at 68.58 88.9 90)
@@ -2222,7 +2419,7 @@
 				)
 			)
 		)
-		(property "MPN" "0402WGF1002TCE"
+		(property "MPN" "RC0402FR-0710KL"
 			(at 0 0 0)
 			(hide yes)
 			(show_name no)
@@ -2233,7 +2430,7 @@
 				)
 			)
 		)
-		(property "Manufacturer" "UNI-ROYAL"
+		(property "Manufacturer" "YAGEO"
 			(at 0 0 0)
 			(hide yes)
 			(show_name no)
@@ -2244,7 +2441,7 @@
 				)
 			)
 		)
-		(property "LCSC" "C25744"
+		(property "LCSC" "C60490"
 			(at 0 0 0)
 			(hide yes)
 			(show_name no)
@@ -2396,7 +2593,7 @@
 	)
 	(symbol
 		(lib_id "power:GND")
-		(at 54.61 86.36 0)
+		(at 38.1 100.33 0)
 		(unit 1)
 		(body_style 1)
 		(exclude_from_sim no)
@@ -2406,7 +2603,7 @@
 		(dnp no)
 		(uuid "48052d59-dcf9-4791-9862-00c7a87de3b8")
 		(property "Reference" "#PWR0tvs12v01"
-			(at 58.42 86.36 0)
+			(at 41.91 100.33 0)
 			(hide yes)
 			(show_name no)
 			(do_not_autoplace no)
@@ -2417,7 +2614,7 @@
 			)
 		)
 		(property "Value" "GND"
-			(at 55.372 86.36 0)
+			(at 38.1 104.394 0)
 			(show_name no)
 			(do_not_autoplace no)
 			(effects
@@ -2427,7 +2624,7 @@
 			)
 		)
 		(property "Footprint" ""
-			(at 54.61 86.36 0)
+			(at 38.1 100.33 0)
 			(show_name no)
 			(do_not_autoplace no)
 			(effects
@@ -2437,7 +2634,7 @@
 			)
 		)
 		(property "Datasheet" ""
-			(at 54.61 86.36 0)
+			(at 38.1 100.33 0)
 			(show_name no)
 			(do_not_autoplace no)
 			(effects
@@ -2447,7 +2644,7 @@
 			)
 		)
 		(property "Description" "Power symbol creates a global label with name \"GND\" , ground"
-			(at 54.61 86.36 0)
+			(at 38.1 100.33 0)
 			(hide yes)
 			(show_name no)
 			(do_not_autoplace no)
@@ -2546,7 +2743,7 @@
 	)
 	(symbol
 		(lib_id "power:GND")
-		(at 38.1 105.41 0)
+		(at 68.58 57.15 0)
 		(unit 1)
 		(body_style 1)
 		(exclude_from_sim no)
@@ -2556,7 +2753,7 @@
 		(dnp no)
 		(uuid "5526d125-8107-4dba-85ca-4b5826ea8f92")
 		(property "Reference" "#PWR0tvs01"
-			(at 41.91 105.41 0)
+			(at 72.39 57.15 0)
 			(hide yes)
 			(show_name no)
 			(do_not_autoplace no)
@@ -2567,7 +2764,7 @@
 			)
 		)
 		(property "Value" "GND"
-			(at 38.862 105.41 0)
+			(at 69.342 57.15 0)
 			(show_name no)
 			(do_not_autoplace no)
 			(effects
@@ -2577,7 +2774,7 @@
 			)
 		)
 		(property "Footprint" ""
-			(at 38.1 105.41 0)
+			(at 68.58 57.15 0)
 			(show_name no)
 			(do_not_autoplace no)
 			(effects
@@ -2587,7 +2784,7 @@
 			)
 		)
 		(property "Datasheet" ""
-			(at 38.1 105.41 0)
+			(at 68.58 57.15 0)
 			(show_name no)
 			(do_not_autoplace no)
 			(effects
@@ -2597,7 +2794,7 @@
 			)
 		)
 		(property "Description" "Power symbol creates a global label with name \"GND\" , ground"
-			(at 38.1 105.41 0)
+			(at 68.58 57.15 0)
 			(hide yes)
 			(show_name no)
 			(do_not_autoplace no)
@@ -2918,7 +3115,7 @@
 	)
 	(symbol
 		(lib_id "power:GND")
-		(at 96.52 95.25 0)
+		(at 24.13 100.33 0)
 		(unit 1)
 		(body_style 1)
 		(exclude_from_sim no)
@@ -2928,7 +3125,7 @@
 		(dnp no)
 		(uuid "ef19b682-da4b-4509-b903-3029f0beaedf")
 		(property "Reference" "#PWR0d01"
-			(at 96.52 99.06 0)
+			(at 24.13 104.14 0)
 			(hide yes)
 			(show_name no)
 			(do_not_autoplace no)
@@ -2939,7 +3136,7 @@
 			)
 		)
 		(property "Value" "GND"
-			(at 96.52 99.314 0)
+			(at 24.13 104.394 0)
 			(show_name no)
 			(do_not_autoplace no)
 			(effects
@@ -2949,7 +3146,7 @@
 			)
 		)
 		(property "Footprint" ""
-			(at 96.52 95.25 0)
+			(at 24.13 100.33 0)
 			(show_name no)
 			(do_not_autoplace no)
 			(effects
@@ -2959,7 +3156,7 @@
 			)
 		)
 		(property "Datasheet" ""
-			(at 96.52 95.25 0)
+			(at 24.13 100.33 0)
 			(show_name no)
 			(do_not_autoplace no)
 			(effects
@@ -2969,7 +3166,7 @@
 			)
 		)
 		(property "Description" "Power symbol creates a global label with name \"GND\" , ground"
-			(at 96.52 95.25 0)
+			(at 24.13 100.33 0)
 			(hide yes)
 			(show_name no)
 			(do_not_autoplace no)
@@ -2993,7 +3190,7 @@
 	)
 	(symbol
 		(lib_id "Device:D_Zener")
-		(at 50.8 86.36 0)
+		(at 38.1 91.44 270)
 		(unit 1)
 		(body_style 1)
 		(exclude_from_sim no)
@@ -3003,7 +3200,7 @@
 		(dnp no)
 		(uuid "f1ace983-18bf-4781-be5e-b6b0e761dbc3")
 		(property "Reference" "D3"
-			(at 50.8 82.55 0)
+			(at 41.91 91.44 0)
 			(show_name no)
 			(do_not_autoplace no)
 			(effects
@@ -3013,7 +3210,7 @@
 			)
 		)
 		(property "Value" "SMAJ12A"
-			(at 50.8 90.17 0)
+			(at 34.29 91.44 0)
 			(show_name no)
 			(do_not_autoplace no)
 			(effects
@@ -3023,7 +3220,7 @@
 			)
 		)
 		(property "Footprint" "Diode_SMD:D_SMA"
-			(at 50.8 86.36 0)
+			(at 38.1 91.44 0)
 			(hide yes)
 			(show_name no)
 			(do_not_autoplace no)
@@ -3034,7 +3231,7 @@
 			)
 		)
 		(property "Datasheet" ""
-			(at 50.8 86.36 0)
+			(at 38.1 91.44 0)
 			(hide yes)
 			(show_name no)
 			(do_not_autoplace no)
@@ -3045,7 +3242,7 @@
 			)
 		)
 		(property "Description" "12V unidirectional TVS, 400W (10/1000us), clamps 12V_EXI (SP1 pin 5) against surge/ESD; K (cathode) to rail, A (anode) to GND"
-			(at 50.8 86.36 0)
+			(at 38.1 91.44 0)
 			(hide yes)
 			(show_name no)
 			(do_not_autoplace no)
@@ -3056,7 +3253,7 @@
 			)
 		)
 		(property "MPN" "SMAJ12A"
-			(at 50.8 86.36 0)
+			(at 38.1 91.44 0)
 			(hide yes)
 			(show_name no)
 			(do_not_autoplace no)
@@ -3067,7 +3264,7 @@
 			)
 		)
 		(property "Manufacturer" "Hongjiacheng"
-			(at 50.8 86.36 0)
+			(at 38.1 91.44 0)
 			(hide yes)
 			(show_name no)
 			(do_not_autoplace no)
@@ -3078,7 +3275,7 @@
 			)
 		)
 		(property "LCSC" "C19077531"
-			(at 50.8 86.36 0)
+			(at 38.1 91.44 0)
 			(hide yes)
 			(show_name no)
 			(do_not_autoplace no)

hardware/re-bba-rb/fp-lib-table

@@ -1,6 +1,5 @@
 (fp_lib_table
 	(version 7)
-	(lib (name "gc") (type "KiCad") (uri "${KIPRJMOD}/gc.pretty") (options "") (descr ""))
 	(lib (name "hardware") (type "KiCad") (uri "${KIPRJMOD}/..") (options "") (descr ""))
 	(lib (name "sp1_test_plug") (type "KiCad") (uri "${KIPRJMOD}/../sp1_test_plug") (options "") (descr ""))
 )

hardware/re-bba-rb/re-bba-rb.kicad_pro

@@ -543,6 +543,25 @@
         "via_drill": 0.3,
         "wire_width": 6
       },
+      {
+        "bus_width": 12,
+        "clearance": 0.15,
+        "diff_pair_gap": 0.25,
+        "diff_pair_via_gap": 0.25,
+        "diff_pair_width": 0.2,
+        "line_style": 0,
+        "microvia_diameter": 0.3,
+        "microvia_drill": 0.1,
+        "name": "LED",
+        "pcb_color": "rgba(0, 0, 0, 0.000)",
+        "priority": 1,
+        "schematic_color": "rgba(0, 0, 0, 0.000)",
+        "track_width": 0.15,
+        "tuning_profile": "",
+        "via_diameter": 0.6,
+        "via_drill": 0.3,
+        "wire_width": 6
+      },
       {
         "bus_width": 12,
         "clearance": 0.15,
@@ -687,6 +706,50 @@
       {
         "netclass": "USB_DP",
         "pattern": "*FT_DN*"
+      },
+      {
+        "netclass": "LED",
+        "pattern": "/fpga/LED_G"
+      },
+      {
+        "netclass": "LED",
+        "pattern": "/fpga/LED_R"
+      },
+      {
+        "netclass": "LED",
+        "pattern": "*D6-A*"
+      },
+      {
+        "netclass": "LED",
+        "pattern": "*D7-A*"
+      },
+      {
+        "netclass": "LED",
+        "pattern": "*D8-A*"
+      },
+      {
+        "netclass": "LED",
+        "pattern": "*D8-K*"
+      },
+      {
+        "netclass": "LED",
+        "pattern": "*D9-A*"
+      },
+      {
+        "netclass": "LED",
+        "pattern": "*D11-K*"
+      },
+      {
+        "netclass": "LED",
+        "pattern": "*D12-K*"
+      },
+      {
+        "netclass": "LED",
+        "pattern": "*D13-K*"
+      },
+      {
+        "netclass": "LED",
+        "pattern": "*Q2-C*"
       }
     ]
   },

hardware/re-bba-rb/re-bba-rb.kicad_sch

@@ -1239,7 +1239,7 @@
 	)
 	(sheet
 		(at 189.23 96.52)
-		(size 34.925 61.976)
+		(size 34.925 51.435)
 		(exclude_from_sim no)
 		(in_bom yes)
 		(on_board yes)
@@ -1265,7 +1265,7 @@
 			)
 		)
 		(property "Sheetfile" "ethernet.kicad_sch"
-			(at 189.23 159.0806 0)
+			(at 189.23 148.5396 0)
 			(show_name no)
 			(do_not_autoplace no)
 			(effects