Bring-up: W5100 bus self-test, eFuse OVLO bug, Pi SPI EXI host

From the physical V2 bring-up session (2026-09-20):

- exi_bba/w5100_selftest.py (NEW): standalone FPGA<->W5100 bus diagnostic.
  Clock-independent data-bus walk (direct-mode GAR0 read-back, all 8 lines) +
  MR software-reset self-clear (needs the 25 MHz crystal). Reports 4 verdicts on
  D6/D7 LEDs AND over UART (115200): GOOD / data-line-N / clock-dead / no-response.
  Boot wait is 85 ms (> the W5100S 60.3 ms init). On this board: GOOD -- bus +
  all 8 data lines + 25 MHz clock all verified (unlike V1's broken D3).

- REVIEW.md / TODO.md: eFuse U13 OVLO is tied to GND, which on the TPS25961
  selects the internal FIXED ~6 V overvoltage cutoff -- so it blocks the 12 V
  rail entirely (bench-confirmed: 12V_EXI=0, GC_ON=0, W5100 unpowered). FAB-
  BLOCKER for V2.1: fix with an OVLO divider (~1.1M/100k -> trip ~15 V). Bench
  workaround: lift U13 pin 2 (OVLO) off GND. Also closed the eFuse-placement,
  GND-via/3V3-zone, and CC-ESD TODO items.

- hardware/re-bba-rb/exi_devid_spi.py (NEW): Pi hardware-SPI (~25 MHz) EXI
  device-ID host, companion to the bit-bang exi_devid_rpi.py.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>

hardware/re-bba-rb/REVIEW.md

@@ -308,6 +308,19 @@ datasheet extraction, WebSearch/WebFetch for parts and reference designs.
       EFUSE_EN : R46, R47, U13.5 EN/UVLO
       EFUSE_ILIM: R45, U13.3 ILIM
       GND      : U13.2 OVLO, U13.4 GND, R45.2, R47.2, C66.2
+  ⚠️ **BUG FOUND AT BRING-UP 2026-09-16 — this OVLO=GND is WRONG for a 12 V
+  rail and the eFuse passes NOTHING.** Per the TPS25961 datasheet, tying OVLO to
+  GND selects the *internal fixed* overvoltage threshold **VOVP(R) = 5.98 V typ
+  (5.55–6.5 V)** — NOT "OVLO disabled". A 12 V input is far above that, so the
+  device sits in overvoltage lockout with the FET off (bench-confirmed: 12V_EXI =
+  0 V, GC_ON = 0 V, W5100 unpowered). The earlier review note ("OVLO tied to GND
+  for the internal fixed threshold, abs max 6.5 V fine") caught the pin abs-max
+  but MISSED that the fixed VIN cutoff is ~6 V. **Fix (V2.1):** drive OVLO from a
+  divider off 12V_RAW so the trip sits ~14–16 V (above 12 V, below the 19 V max /
+  the D3 clamp): e.g. **R_top ≈ 1.1 MΩ (12V_RAW→OVLO) + R_bottom ≈ 100 kΩ
+  (OVLO→GND)** → OVLO pin = 1.24 V at ~15 V VIN, and ~1.0 V at 12 V (stays on).
+  BENCH WORKAROUND to keep bring-up moving: inject 12 V straight onto 12V_EXI
+  (C65+ pad or U3.3 VIN), bypassing the mis-set eFuse.
   **D3 (SMAJ12A TVS) stays on the INPUT side on purpose** — it clamps
   GC-side surges before they reach the eFuse's 21 V absolute maximum. **C65
   is on the OUTPUT side on purpose** — it is the bulk cap whose inrush we are