finalized pcb design, need to remeasure PCB outline.

exi_bba/bba_top.py

@@ -2,7 +2,10 @@
 
 Clock domains
 -------------
-capture  : 54 MHz, from 12 MHz crystal via SB_PLL40_PAD (DIVR=0 DIVF=71 DIVQ=4)
+capture  : 54 MHz, from 12 MHz oscillator via SB_PLL40_CORE (REFERENCECLK fed
+           from a global-buffer input pin; DIVR=0 DIVF=71 DIVQ=4).  CORE (not
+           PAD) so the reference clock is not tied to the dedicated PLL pad — it
+           enters on a clock-capable GBIN pin, leaving board routing free.
 exi/sync : 24 MHz, from the iCE40UP5K internal SB_HFOSC (÷2, CLKHF_DIV=0b01)
 
 Submodule instantiation and signal wiring
@@ -119,15 +122,14 @@ class BBATop(Elaboratable):
             # ~91 MHz on this device; the byte-FIFO read path brings the
             # integrated capture domain to ~62 MHz, so 54 closes with margin.
             m.domains += ClockDomain("capture")
-            platform.lookup(platform.default_clk).attrs["GLOBAL"] = False
             m.submodules.pll = Instance(
-                "SB_PLL40_PAD",
+                "SB_PLL40_CORE",
                 p_FEEDBACK_PATH = "SIMPLE",
                 p_DIVR          = 0,
                 p_DIVF          = 71,
                 p_DIVQ          = 4,
                 p_FILTER_RANGE  = 1,
-                i_PACKAGEPIN    = platform.request("clk12", dir="-").io,
+                i_REFERENCECLK  = platform.request("clk12").i,
                 i_RESETB        = Const(1, 1),
                 i_BYPASS        = Const(0, 1),
                 o_PLLOUTGLOBAL  = ClockSignal("capture"),

exi_bba/synth.py

@@ -41,7 +41,7 @@ class IceBreakerPlatform(LatticeICE40Platform):
 
     resources = [
         Resource("clk12", 0,
-                 Pins("35", dir="i"),
+                 Pins("20", dir="i"),
                  Clock(12e6),
                  Attrs(GLOBAL=True, IO_STANDARD="SB_LVCMOS")),
 
@@ -62,7 +62,7 @@ class IceBreakerPlatform(LatticeICE40Platform):
                  Subsignal("rd_n",  Pins("19", dir="o")),
                  Subsignal("wr_n",  Pins("26", dir="o")),
                  Subsignal("int_n", Pins("23", dir="i")),
-                 Subsignal("rst_n", Pins("20", dir="o")),
+                 Subsignal("rst_n", Pins("18", dir="o")),
                  Attrs(IO_STANDARD="SB_LVCMOS")),
 
         # Bring-up status panel → iCEbreaker ONBOARD parts (dedicated pins, not