finalized pcb design, need to remeasure PCB outline.

exi_bba/synth.py

@@ -41,7 +41,7 @@ class IceBreakerPlatform(LatticeICE40Platform):
 
     resources = [
         Resource("clk12", 0,
-                 Pins("35", dir="i"),
+                 Pins("20", dir="i"),
                  Clock(12e6),
                  Attrs(GLOBAL=True, IO_STANDARD="SB_LVCMOS")),
 
@@ -62,7 +62,7 @@ class IceBreakerPlatform(LatticeICE40Platform):
                  Subsignal("rd_n",  Pins("19", dir="o")),
                  Subsignal("wr_n",  Pins("26", dir="o")),
                  Subsignal("int_n", Pins("23", dir="i")),
-                 Subsignal("rst_n", Pins("20", dir="o")),
+                 Subsignal("rst_n", Pins("18", dir="o")),
                  Attrs(IO_STANDARD="SB_LVCMOS")),
 
         # Bring-up status panel → iCEbreaker ONBOARD parts (dedicated pins, not