From 6ce7657f053c6bf4eab589a33e4313f1808ea948 Mon Sep 17 00:00:00 2001 From: Dennis Brentjes Date: Fri, 2 Oct 2026 08:44:48 +0000 Subject: [PATCH] eFuse V2.1 fix: datasheet-derived OVLO ladder + ILIM correction Works the TPS25961 fix out from the datasheet rather than from memory, and re-solves it against resistors already on the BOM. OVLO: TI's 3-resistor ladder (eq 7/8) -> R46 620k->150k, R47 100k->10k, new R48 12k + R49 2.2k (=14.2k). UVLO 8.93 V typ, unchanged from today; OVLO 15.21 V typ, 15.81 V worst case. The OVLO ceiling is set by U3 (TPS562201, 4.5-17 V input), not by the eFuse -- that rules out a tempting 3-resistor solution tripping at 17.24 V. ILIM: R45 100k -> 33k. 0.516 A sat BELOW the board's own 621 mA inrush, so the part entered current limiting on every power-on (-> thermal shutdown -> retries -> latch-off). Inrush control comes from the fixed 5.17 V/ms slew rate, not ILIM, so raising ILIM costs no inrush protection; it is pure fault protection at ~27x the measured 56 mA load. Every value is already stocked and 620k loses its only user: one FEWER unique part, +2 placements. Co-Authored-By: Claude Opus 5 --- hardware/re-bba-rb/REVIEW.md | 60 ++++++++++++++++++++++++++++++------ hardware/re-bba-rb/TODO.md | 23 +++++++++++--- 2 files changed, 69 insertions(+), 14 deletions(-) diff --git a/hardware/re-bba-rb/REVIEW.md b/hardware/re-bba-rb/REVIEW.md index 02c9662..5afb691 100644 --- a/hardware/re-bba-rb/REVIEW.md +++ b/hardware/re-bba-rb/REVIEW.md @@ -315,10 +315,34 @@ datasheet extraction, WebSearch/WebFetch for parts and reference designs. device sits in overvoltage lockout with the FET off (bench-confirmed: 12V_EXI = 0 V, GC_ON = 0 V, W5100 unpowered). The earlier review note ("OVLO tied to GND for the internal fixed threshold, abs max 6.5 V fine") caught the pin abs-max - but MISSED that the fixed VIN cutoff is ~6 V. **Fix (V2.1):** drive OVLO from a - divider off 12V_RAW so the trip sits ~14–16 V (above 12 V, below the 19 V max / - the D3 clamp): e.g. **R_top ≈ 1.1 MΩ (12V_RAW→OVLO) + R_bottom ≈ 100 kΩ - (OVLO→GND)** → OVLO pin = 1.24 V at ~15 V VIN, and ~1.0 V at 12 V (stays on). + but MISSED that the fixed VIN cutoff is ~6 V. + + **FIX (V2.1), datasheet-derived 2026-10-02** — TI's 3-resistor ladder + (§8.2.3.2) from 12V_RAW to GND, EN/UVLO tapped at R1–R2 and OVLO at R2–R3: + VIN(UV) = VUVLO(R) × (R1+R2+R3)/(R2+R3) (eq 7) + VIN(OV) = VOVLO(R) × (R1+R2+R3)/R3 (eq 8), both thresholds 1.24 V + | ref | was | becomes | LCSC | already on board as | + |---|---|---|---|---| + | R46 (R1, 12V_RAW→EN/UVLO) | 620 k | **150 k** | C93947 | R3 | + | R47 (R2, EN/UVLO→OVLO) | 100 k | **10 k** | C25744 | R2, R9, R11, … | + | R48 (R3a, OVLO→GND) NEW | — | **12 k** | C25752 | R10 | + | R49 (R3b, series w/ R48) NEW | — | **2.2 k** | C25879 | R30 | + R3 = 12 k + 2.2 k = 14.2 kΩ. Results across tolerance (VOVLO 1.20/1.24/1.27): + **UVLO 8.93 V typ (8.64–9.14)** — identical to the current board, so turn-on + behaviour is unchanged — and **OVLO 15.21 V typ (14.72–15.58)**, worst case + with 1% resistors **15.81 V**. String current 68.9 µA at 12 V (TI requires + ≥20× the 0.1 µA pin leakage, i.e. ≥2 µA). OVLO pin sits at 0.98 V at 12 V and + 1.55 V at 19 V — far under its 6.5 V abs max, the lowest-rated pin on the part. + + **The OVLO ceiling is set by U3, not by the eFuse.** The TPS562201 buck is + rated **4.5–17 V** input (19 V abs max), so OVLO must disconnect before the + buck is overstressed. This rules out an otherwise attractive 3-resistor + solution (150 k/10 k/12.4 k) that trips at 17.24 V typ / ~18 V worst case — + it would leave U3 running out of spec. Do not "simplify" to that. + + **Cost:** every value above is already on the BOM, and 620 k (C137952) had + R46 as its only user, so it drops out — **net one FEWER unique part**, +2 + placements. BENCH WORKAROUND to keep bring-up moving: inject 12 V straight onto 12V_EXI (C65+ pad or U3.3 VIN), bypassing the mis-set eFuse. **D3 (SMAJ12A TVS) stays on the INPUT side on purpose** — it clamps @@ -332,12 +356,28 @@ datasheet extraction, WebSearch/WebFetch for parts and reference designs. dV/dt = 5.17 V/ms (fixed, typical) ⇒ I = C·dV/dt = 120 µF × 5.17 V/ms = **621 mA** over a 2.3 ms ramp. R_ILIM only matters if it is set *below* that figure. - - **R45 = 100 kΩ ⇒ I_LIM ≈ 500 mA** (datasheet Equation 6: R_ILIM = - 50000/I_LIM; 100 kΩ is one of TI's own characterised points, 0.516 A typ, - ±18% ⇒ 0.42–0.61 A). This both caps inrush at 500 mA and gives **3.8× - headroom** over the ~130 mA steady-state 12 V draw. 100 kΩ is deliberately - inside a valid ON-resistance bin — **Table 7-1 forbids 58.8–66.7 kΩ, - 111–142 kΩ and 250–500 kΩ**; do not "round" R45 into those bands. + - ⚠️ **R45 = 100 kΩ ⇒ I_LIM ≈ 0.516 A typ (0.42–0.61 A) is WRONG — it sits + BELOW this board's own 621 mA inrush.** The consequence is that the part + enters active current limiting on *every* power-on; sustained current + limiting drives thermal shutdown → 3 auto-retries → latch-off. **Change to + R45 = 33 kΩ (C25779, already on the board as R1/R39/R40) ⇒ 1.52 A typ + (1.24–1.79 A)**, which clears the inrush even if the slew rate runs 30% + fast (0.81 A). + **Inrush protection does NOT come from ILIM — it comes from the fixed + 5.17 V/ms output slew rate**, which ramps the rail in 2.3 ms at 621 mA + regardless of the ILIM setting. (The TPS25961DRV is 6-pin: OUT/OVLO/ILIM/ + GND/EN·UVLO/IN — there is NO dVdt pin, so the slew rate cannot be changed; + the only other lever on inrush is reducing C65.) ILIM is therefore pure + fault protection, and 1.52 A is ~27× the measured 56 mA load while staying + far inside the console's 3.25 A supply. + Measured 2026-10-02: the board draws **0.67 W at 12 V ≈ 56 mA** with the + link up — about half the 130 mA originally budgeted. Note the W5100S spec + is per LINK STATE, not traffic (100M Link 93 mA typ / 110 mA max vs Unlink + 40 mA): in 100BASE-TX the PHY drives idle symbols continuously, so an idle + measurement with the link up already includes the dominant load and running + traffic adds very little. + **Table 7-1 forbids 58.8–66.7 kΩ, 111–142 kΩ and 250–500 kΩ** — 33 kΩ is + clear of all three; do not "round" R45 into those bands. - **Startup dissipation is safe**: FET energy = ½CV² = **8.65 mJ** regardless of ramp rate ⇒ ~3.0 W average over 2.9 ms. Figure 6-31 puts time-to-thermal- shutdown at ~3 W far beyond 100 ms. Steady-state loss is 106 mΩ × 0.13² = diff --git a/hardware/re-bba-rb/TODO.md b/hardware/re-bba-rb/TODO.md index ba28123..f7f6743 100644 --- a/hardware/re-bba-rb/TODO.md +++ b/hardware/re-bba-rb/TODO.md @@ -245,10 +245,25 @@ schematic changes. 2026-09-16, FAB-BLOCKER for V2.1).** OVLO (pin 2) is tied to GND, which on the TPS25961 selects the internal *fixed* overvoltage cutoff ~5.98 V — so a 12 V rail is permanently in overvoltage lockout and the eFuse passes - nothing (bench-confirmed: 12V_EXI=0, GC_ON=0, W5100 unpowered). **Fix:** - OVLO divider off 12V_RAW, R_top ≈ 1.1 M / R_bottom ≈ 100 k → trip ~15 V. - See REVIEW.md eFuse entry. Bench workaround: feed 12 V onto 12V_EXI (C65+ / - U3 VIN) to bypass it. This must be fixed before any V2.1 fab order. + nothing (bench-confirmed: 12V_EXI=0, GC_ON=0, W5100 unpowered). + **FIX WORKED OUT FROM THE DATASHEET 2026-10-02 — values final, needs + schematic + PCB work.** TI 3-resistor ladder (§8.2.3.2), EN/UVLO tapped at + R1–R2 and OVLO at R2–R3, plus an ILIM correction: + R46 620 k -> **150 k** (C93947) R1, top: 12V_RAW -> EN/UVLO + R47 100 k -> **10 k** (C25744) R2: EN/UVLO -> OVLO + R48 NEW -> **12 k** (C25752) \ R3 = 14.2 k in series, + R49 NEW -> **2.2 k** (C25879) / OVLO -> GND + R45 100 k -> **33 k** (C25779) ILIM 0.52 A -> 1.52 A + U13 pin 2 (OVLO): disconnect from GND, wire to the R47/R48 junction. + Gives UVLO 8.93 V typ (unchanged from today) and OVLO 15.21 V typ, + 15.81 V worst case — under U3's 17 V input rating, which is what actually + caps the OVLO target. ILIM must exceed the board's own 621 mA inrush; + 0.52 A did not, so the part current-limited on every power-on. + **Every value is already on the BOM and 620 k loses its only user, so this + is one FEWER unique part, +2 placements.** Full derivation, tolerance + analysis and the rejected alternatives are in REVIEW.md §eFuse. + Bench workaround meanwhile: feed 12 V onto 12V_EXI (C65+ / U3 VIN), or + lift U13 pin 2 (done on the lab unit). Must be fixed before any V2.1 fab. - [x] **D9 "USB" LED dark — OPEN SOLDER JOINT on its anode pad — FIXED by reflow 2026-09-30. Assembly defect on this unit, NOT a design bug.** Symptom: D9 never lights, on USB-only or GC power. Measured 3V3 on the