Launch MISO a full cycle early instead of chasing delay

PHASE_METER on a console settled what two rounds of delay-cutting could not.
Per-speed dump, first two slots per EXI speed index, with the register file
and both byte FIFOs out of the MISO path:

  0:8080  1:8080  2:8080  3:8080  4:8080  5:C040

Perfect to 16 MHz, one bit late at 27 MHz.  The 8-slot dump at 27 MHz read
C0 40 40 40 C0 40 40 40 -- a UNIFORM one-bit lag (ones at bits 1, 9, 17, 25,
33, ...), with extra highs at bits 0 and 32 where libogc splits the read into
two 4-byte transfers and MISO tri-states to its pull-up in the gap.  The ID
dump agreed exactly.

Decisive detail: ~9 ns had already been removed from the fabric output path
(the EXI_J4 pad merge, then the CS mux, then the entire fabric route by moving
the output into an SB_IO register) and the hardware result stayed BYTE
IDENTICAL each time.  Nine nanoseconds out of an 18.5 ns budget cannot change
nothing if propagation were the whole story.  What is left is the part no RTL
change can reach: input pad + GLOBAL CLOCK NETWORK INSERTION + IOB clock-to-Q
+ output pad, plus the host's own setup.  There was no fabric delay left to
cut, so cutting delay was the wrong move.

So double the budget instead.  MISO is now launched on the RISING edge
carrying the bit the host will sample at the NEXT rising edge, so the whole
path gets a FULL period (37 ns at 27 MHz) rather than half.  This is safe in
both directions: the insertion delay that caused the problem now covers the
host's hold time on the previous bit, and a full period covers its setup.

  - tx_out is clocked on the rising edge and loads at rx_bit == 7, one
    bit-time earlier than a falling-edge shifter loading at rx_bit == 0.
  - tx_hold and the entire exiclk_n domain are gone: the engine now has ONE
    clock edge and ONE phase reference.
  - synth.py's SB_IO output register moves to NEG_TRIGGER=0.
  - Byte alignment is unchanged -- T2/T5 still land A5 and 3C in the same
    slots.  Only the sub-bit launch timing moved.

Testbench consequence, and it matters: bba_top's master sampled MISO AFTER
raising the clock.  With a zero-delay simulation and a rising-edge launch that
reads the NEXT bit, so the suite would have reported everything one bit early
while hardware was correct.  Both masters now sample in the CLK-LOW phase --
the value the host latches ON the rising edge -- which is also exactly what
the hardware notes say a probe must do.

T2 slot 0 now reads 0xFF (the CS-reset parking value that keeps MISO high
while deselected) instead of 0x00; it is a header byte the host ignores.
T6 re-anchored to the rising edge and still proves miso_next predicts
spi_miso bit for bit, so the SB_IO register stays equivalent to the fabric
model rather than an untested divergence.

--seeds 8: clk 28.9-32.1 MHz, EXI 62.1-65.4 MHz, 8/8 PASS.  The EXI numbers
rise sharply (41.6-49.7 -> 62.1-65.4) because the setup path into the IOB
register is now posedge->posedge against a FULL period instead of
posedge->negedge against a half -- the same doubling, visible internally.
Best seed 3 (clk 32.09, EXI 62.78), flashed.

Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>

exi_bba/bba_top.py

@@ -434,8 +434,13 @@ if __name__ == "__main__":
             ctx.set(dut.exi_clk, 0)                      # falling: master drives
             ctx.set(dut.exi_mosi, (mosi_val >> bit) & 1)
             await ctx.delay(HP * (HALF))
-            ctx.set(dut.exi_clk, 1)                      # rising: both sample
+            # Sample MISO in the CLK-LOW phase -- the value the host latches
+            # ON the rising edge.  The device launches MISO one bit EARLY, on
+            # the rising edge (see spi_mode3_slave), so reading AFTER raising
+            # the clock here would see the NEXT bit and the testbench would
+            # report everything one bit early while hardware was correct.
             miso = (miso << 1) | ctx.get(dut.exi_miso)
+            ctx.set(dut.exi_clk, 1)                      # rising: device samples
             await ctx.delay(HP * (HALF))
         return miso