Initial commit

2025-09-14 19:55:43 +02:00
commit 7b5ecda692
17 changed files with 361 additions and 0 deletions
@@ -0,0 +1 @@
+build
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+from amaranth import *
+
+class LEDBlinker(Elaboratable):
+    def elaborate(self, platform):
+        m = Module()
+
+        cd_sync = ClockDomain("sync")
+        m.domains += cd_sync
+        platform.lookup(platform.default_clk).attrs['GLOBAL'] = False
+
+        locked = Signal()
+        pllout = Signal()
+
+        m.submodules.pll = Instance("SB_PLL40_PAD",
+            p_FEEDBACK_PATH = "SIMPLE",
+            p_DIVR          = 0,
+            p_DIVF          = 7,
+            p_DIVQ          = 1,
+            p_FILTER_RANGE  = 1,
+            
+            o_LOCK          = locked,
+            i_RESETB        = 1,
+            i_BYPASS        = 0,
+            i_PACKAGEPIN    = platform.request("clk12", dir="-").io,
+            o_PLLOUTCORE    = cd_sync.clk
+        )
+
+        ledr0 = platform.request("led_r")
+        ledg0 = platform.request("led_g")
+
+        ledr1 = platform.request("led_r", 1)
+        ledg1 = platform.request("led_g", 1)
+        ledg2 = platform.request("led_g", 2)
+        ledg3 = platform.request("led_g", 3)
+        ledg4 = platform.request("led_g", 4)
+
+        half_freq = int(42e6 // 2)
+        timer = Signal(range(half_freq + 1))
+    
+        init = Signal()
+
+        with m.If(init == 0):
+            m.d.sync += ledg0.o.eq(255)
+            m.d.sync += init.eq(1)
+        
+        with m.If(timer == half_freq):
+            m.d.sync += ledr0.o.eq(~ledr0.o)
+            m.d.sync += ledg0.o.eq(~ledg0.o)
+            m.d.sync += timer.eq(0)
+        with m.Else():
+            m.d.sync += timer.eq(timer + 1)
+
+        return m
+
+from amaranth_boards.icebreaker import ICEBreakerPlatform
+from amaranth.vendor import SiliconBluePlatform;
+
+platform = ICEBreakerPlatform()
+platform.add_resources(platform.break_off_pmod)
+platform.build(LEDBlinker(), do_program=True, verbose=True, nextpnr_opts='--freq 48')