w5100/w5500: annotate the intentionally-unreferenced register map

An AST audit for dead code flags seven register-address constants that nothing
in the tree references.  They are staying, and the files now say why at the
point of definition, so the next audit does not re-litigate them: the map costs
no logic and is kept COMPLETE on purpose, because three separate hardware bugs
came out of guessing it (the 0x4000-vs-0x8000 buffer base, NETLCKR, and the
60.3 ms settle).  A partial map invites re-guessing the missing half.  _TMSR in
particular documents where the second byte of the RMSR/TMSR = 0x55 burst lands.

Also fixed a real readability defect found while reading them: _RST_LOW_DEFAULT
and its two-line comment sat WEDGED BETWEEN _NETLCKR and the continuation of
_NETLCKR's own comment, so the sentence explaining the network lock finished on
the line declaring _NETLCK_UNLOCK.  NETLCKR's note is now whole and in one
place, and _RST_LOW_DEFAULT sits after the register map with the 60.3 ms settle
mentioned alongside it, since the two waits are easy to confuse.

VERIFIED: generated RTLIL identical (9874 lines), so this is comment-only.
Both masters' testbenches pass.

Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>

exi_bba/w5500_spi_master.py

@@ -44,6 +44,11 @@ _W5500_S0_TX_FSR = 0x0020  # Socket 0 TX Free Size (2 bytes)
 _W5500_S0_TX_WR  = 0x0024  # Socket 0 TX Write Pointer
 _W5500_S0_RX_RSR = 0x0026  # Socket 0 RX Received Size (2 bytes)
 _W5500_S0_RX_RD  = 0x0028  # Socket 0 RX Read Pointer
+
+# ⚠️ _W5500_S0_RXBUF_SIZE, _W5500_S0_TXBUF_SIZE and _W5500_S0_TX_FSR are
+# intentionally unreferenced: the chip's 2 KB-per-socket defaults are what this
+# master uses, and the map is kept complete so nobody has to re-derive the
+# missing half from the datasheet.  They cost no logic.
 _W5500_S0_IMR  = 0x002C   # Socket 0 Interrupt Mask
 
 # Control byte = (BSB << 3) | (RWB << 2) | OM.