Added Uart.
This commit is contained in:
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"""UART debug console (sync domain, 24 MHz).
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Logs key BBA events as short ASCII messages at 115200 baud 8N1 and accepts
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single-byte commands over RX ('r' = force reinit).
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iCEbreaker pin assignments (onboard FT2232H Channel B):
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uart_tx → pin 9 (FPGA → PC)
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uart_rx ← pin 6 (PC → FPGA)
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On the PC, open the second USB serial port at 115200 8N1:
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minicom -D /dev/ttyUSB1 -b 115200 # Linux
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screen /dev/tty.usbserial-XXX1 115200 # macOS
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Events logged
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-------------
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"BBA READY\\r\\n" — one-shot on first clock (bitstream loaded)
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"RST\\r\\n" — NCRA reset issued by the GC
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"ETH UP\\r\\n" — ethernet init complete (rising edge of ready)
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"RX\\r\\n" — ethernet frame received
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"TX\\r\\n" — ethernet frame transmitted
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Commands (single byte on RX)
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-----------------------------
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'r' → one-cycle reinit pulse (caller should re-init the BBA)
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Event overflow: if a second event fires while the sender is busy the
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pending flag is set and the message is queued (one slot per event type).
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Simultaneous rapid-fire events of the same type coalesce to one message.
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"""
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from amaranth import *
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from amaranth.lib.cdc import FFSynchronizer
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__all__ = ["UARTConsole"]
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# ── Message ROM ───────────────────────────────────────────────────────────────
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_MSGS = [
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b"BBA READY\r\n", # 0 EVT_BOOT
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b"RST\r\n", # 1 EVT_RST
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b"ETH UP\r\n", # 2 EVT_READY
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b"RX\r\n", # 3 EVT_RX
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b"TX\r\n", # 4 EVT_TX
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]
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_N = len(_MSGS)
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_ROM = b"".join(_MSGS)
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_START = [sum(len(m) for m in _MSGS[:i]) for i in range(_N)]
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_LEN = [len(m) for m in _MSGS]
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class UARTConsole(Elaboratable):
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"""Bring-up UART console — TX event log + RX command interface.
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All signals are in the sync domain (24 MHz).
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Parameters
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----------
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clk_freq : source clock in Hz (default 24 MHz)
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baud_rate : UART baud rate (default 115 200)
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"""
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EVT_BOOT = 0
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EVT_RST = 1
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EVT_READY = 2
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EVT_RX = 3
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EVT_TX = 4
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def __init__(self, clk_freq=24_000_000, baud_rate=115_200):
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self._div = round(clk_freq / baud_rate)
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# ── Event inputs (sync domain) ────────────────────────────────────
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self.ncra_rst = Signal() # pulse: GC issued NCRA reset
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self.rx_pulse = Signal() # pulse: ethernet frame received
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self.tx_pulse = Signal() # pulse: ethernet frame sent
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self.ready = Signal() # level: ethernet init complete
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# ── Outputs ───────────────────────────────────────────────────────
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self.reinit = Signal() # pulse: 'r' received → caller re-inits
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# ── UART pins (connect directly to platform resources) ────────────
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self.uart_tx = Signal(init=1) # idle high
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self.uart_rx = Signal(init=1)
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def elaborate(self, platform):
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m = Module()
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div = self._div
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# ── Message ROM (compile-time constant array) ─────────────────────
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rom = Array([Const(b, 8) for b in _ROM])
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# ── Event detection ───────────────────────────────────────────────
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pending = Signal(_N)
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boot_done = Signal()
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ready_r = Signal()
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# Boot: fire once on the first clock after reset
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with m.If(~boot_done):
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m.d.sync += [pending[self.EVT_BOOT].eq(1), boot_done.eq(1)]
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# Rising edge of ready → "ETH UP" (log once per init cycle)
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m.d.sync += ready_r.eq(self.ready)
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with m.If(self.ncra_rst):
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m.d.sync += pending[self.EVT_RST].eq(1)
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with m.If(self.ready & ~ready_r):
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m.d.sync += pending[self.EVT_READY].eq(1)
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with m.If(self.rx_pulse):
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m.d.sync += pending[self.EVT_RX].eq(1)
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with m.If(self.tx_pulse):
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m.d.sync += pending[self.EVT_TX].eq(1)
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# ── UART TX — 8N1 shift register ──────────────────────────────────
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# shreg[0] drives uart_tx. Load: start(0) + data[7:0] + stop(1).
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# Shift right each baud period; fill MSB with 1 (idle level).
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tx_cnt = Signal(range(div))
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tx_bits = Signal(range(11)) # 10 → 0 while sending
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tx_shreg = Signal(10, init=0b1111111111)
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tx_busy = Signal()
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tx_load = Signal()
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tx_byte = Signal(8)
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m.d.comb += [
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tx_busy.eq(tx_bits != 0),
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self.uart_tx.eq(tx_shreg[0]),
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]
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with m.If(tx_load & ~tx_busy):
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m.d.sync += [
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tx_shreg.eq(Cat(Const(0, 1), tx_byte, Const(1, 1))),
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tx_bits.eq(10),
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tx_cnt.eq(div - 1),
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]
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with m.Elif(tx_busy):
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with m.If(tx_cnt == 0):
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m.d.sync += [
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tx_shreg.eq(Cat(tx_shreg[1:], Const(1, 1))),
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tx_bits.eq(tx_bits - 1),
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tx_cnt.eq(div - 1),
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]
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with m.Else():
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m.d.sync += tx_cnt.eq(tx_cnt - 1)
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# ── Message sender FSM ────────────────────────────────────────────
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# In IDLE: pick the highest-priority pending event and load its ROM
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# range. In SEND: stream bytes from ROM through the UART TX one at
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# a time, waiting for the transmitter to become free between bytes.
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rom_ptr = Signal(range(len(_ROM) + 1))
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rom_end = Signal(range(len(_ROM) + 1))
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# Default: tx_load/tx_byte driven only from SEND state
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m.d.comb += [tx_load.eq(0), tx_byte.eq(0)]
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with m.FSM(name="sender"):
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with m.State("IDLE"):
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with m.If(pending[self.EVT_BOOT]):
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m.d.sync += [
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rom_ptr.eq(_START[self.EVT_BOOT]),
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rom_end.eq(_START[self.EVT_BOOT] + _LEN[self.EVT_BOOT]),
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pending[self.EVT_BOOT].eq(0),
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]
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m.next = "SEND"
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with m.Elif(pending[self.EVT_RST]):
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m.d.sync += [
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rom_ptr.eq(_START[self.EVT_RST]),
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rom_end.eq(_START[self.EVT_RST] + _LEN[self.EVT_RST]),
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pending[self.EVT_RST].eq(0),
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]
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m.next = "SEND"
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with m.Elif(pending[self.EVT_READY]):
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m.d.sync += [
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rom_ptr.eq(_START[self.EVT_READY]),
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rom_end.eq(_START[self.EVT_READY] + _LEN[self.EVT_READY]),
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pending[self.EVT_READY].eq(0),
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]
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m.next = "SEND"
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with m.Elif(pending[self.EVT_RX]):
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m.d.sync += [
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rom_ptr.eq(_START[self.EVT_RX]),
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rom_end.eq(_START[self.EVT_RX] + _LEN[self.EVT_RX]),
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pending[self.EVT_RX].eq(0),
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]
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m.next = "SEND"
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with m.Elif(pending[self.EVT_TX]):
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m.d.sync += [
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rom_ptr.eq(_START[self.EVT_TX]),
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rom_end.eq(_START[self.EVT_TX] + _LEN[self.EVT_TX]),
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pending[self.EVT_TX].eq(0),
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]
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m.next = "SEND"
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with m.State("SEND"):
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with m.If(~tx_busy):
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with m.If(rom_ptr == rom_end):
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m.next = "IDLE"
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with m.Else():
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m.d.comb += [tx_load.eq(1), tx_byte.eq(rom[rom_ptr])]
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m.d.sync += rom_ptr.eq(rom_ptr + 1)
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# ── UART RX — 8N1 mid-bit sampling ───────────────────────────────
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# Synchronise the raw pin, detect the start-bit falling edge, then
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# sample each subsequent bit at the centre of its baud period.
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rx_sync = Signal(init=1)
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rx_prev = Signal(init=1)
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rx_cnt = Signal(range(div))
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rx_bits = Signal(range(9))
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rx_shreg = Signal(8)
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rx_byte = Signal(8)
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rx_valid = Signal()
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m.submodules += FFSynchronizer(self.uart_rx, rx_sync, init=1)
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# Default: no valid byte this cycle (overridden in STOP when needed)
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m.d.sync += rx_valid.eq(0)
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with m.FSM(name="rx_fsm"):
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with m.State("IDLE"):
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m.d.sync += rx_prev.eq(rx_sync)
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with m.If(rx_prev & ~rx_sync): # falling edge = start bit
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m.d.sync += rx_cnt.eq(div // 2 - 1)
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m.next = "START"
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with m.State("START"):
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# Wait until the centre of the start bit, then verify it is
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# still low (rules out glitches / false starts).
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with m.If(rx_cnt == 0):
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with m.If(~rx_sync):
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m.d.sync += [rx_cnt.eq(div - 1), rx_bits.eq(7)]
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m.next = "DATA"
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with m.Else():
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m.next = "IDLE"
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with m.Else():
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m.d.sync += rx_cnt.eq(rx_cnt - 1)
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with m.State("DATA"):
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with m.If(rx_cnt == 0):
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# UART sends LSB first; shift new bit into MSB so that
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# after 8 samples rx_shreg[0] = bit-0, rx_shreg[7] = bit-7.
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m.d.sync += [
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rx_shreg.eq(Cat(rx_shreg[1:], rx_sync)),
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rx_cnt.eq(div - 1),
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]
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with m.If(rx_bits == 0):
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m.next = "STOP"
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with m.Else():
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m.d.sync += rx_bits.eq(rx_bits - 1)
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with m.Else():
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m.d.sync += rx_cnt.eq(rx_cnt - 1)
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with m.State("STOP"):
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with m.If(rx_cnt == 0):
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with m.If(rx_sync): # valid stop bit
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m.d.sync += [rx_byte.eq(rx_shreg), rx_valid.eq(1)]
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m.next = "IDLE"
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with m.Else():
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m.d.sync += rx_cnt.eq(rx_cnt - 1)
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# ── Command decoder ───────────────────────────────────────────────
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m.d.sync += self.reinit.eq(0)
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with m.If(rx_valid):
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with m.If(rx_byte == ord('r')):
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m.d.sync += self.reinit.eq(1)
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return m
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# ── Testbench ─────────────────────────────────────────────────────────────────
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if __name__ == "__main__":
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import sys
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from amaranth.sim import Simulator, Period
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CLK_FREQ = 24_000_000
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BAUD_RATE = 115_200
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DIV = round(CLK_FREQ / BAUD_RATE) # 208 cycles per bit
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dut = UARTConsole(clk_freq=CLK_FREQ, baud_rate=BAUD_RATE)
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errors = []
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# ── TX helpers ────────────────────────────────────────────────────────
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async def recv_byte(ctx):
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"""Receive one 8N1 byte from uart_tx. Waits for start bit."""
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# Wait for start bit (falling edge)
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while ctx.get(dut.uart_tx) != 0:
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await ctx.tick()
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# Centre of start bit
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await ctx.tick().repeat(DIV // 2)
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assert ctx.get(dut.uart_tx) == 0, "false start"
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# Sample 8 data bits
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byte = 0
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for i in range(8):
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await ctx.tick().repeat(DIV)
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byte |= ctx.get(dut.uart_tx) << i
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# Stop bit
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await ctx.tick().repeat(DIV)
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assert ctx.get(dut.uart_tx) == 1, "missing stop bit"
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return byte
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async def recv_str(ctx, n):
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return bytes([await recv_byte(ctx) for _ in range(n)])
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# ── RX helper ─────────────────────────────────────────────────────────
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async def send_byte_watch(ctx, val, watch_sig):
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"""Send one 8N1 byte on uart_rx, polling watch_sig every tick.
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Returns True if watch_sig was seen high at any point. The reinit
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pulse fires ~100 cycles before the stop-bit wait completes, so
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a tick-by-tick poll is required to catch it.
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"""
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seen = False
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ctx.set(dut.uart_rx, 0) # start bit
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for _ in range(DIV):
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await ctx.tick()
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if ctx.get(watch_sig): seen = True
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for i in range(8):
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ctx.set(dut.uart_rx, (val >> i) & 1)
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for _ in range(DIV):
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await ctx.tick()
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if ctx.get(watch_sig): seen = True
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ctx.set(dut.uart_rx, 1) # stop bit + margin
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for _ in range(DIV + 4):
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await ctx.tick()
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if ctx.get(watch_sig): seen = True
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return seen
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# ── Tests ─────────────────────────────────────────────────────────────
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async def testbench(ctx):
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ctx.set(dut.uart_rx, 1)
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# T1: boot message fires on first clock
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msg = await recv_str(ctx, len(b"BBA READY\r\n"))
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print(f"T1 boot: {msg!r}")
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if msg != b"BBA READY\r\n":
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errors.append(f"T1 boot: got {msg!r}")
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# T2: pulse ncra_rst → "RST\r\n"
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ctx.set(dut.ncra_rst, 1)
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await ctx.tick()
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ctx.set(dut.ncra_rst, 0)
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msg = await recv_str(ctx, len(b"RST\r\n"))
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print(f"T2 rst: {msg!r}")
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if msg != b"RST\r\n":
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errors.append(f"T2 rst: got {msg!r}")
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# T3: ready rising edge → "ETH UP\r\n"
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ctx.set(dut.ready, 1)
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await ctx.tick()
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msg = await recv_str(ctx, len(b"ETH UP\r\n"))
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print(f"T3 ready: {msg!r}")
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if msg != b"ETH UP\r\n":
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errors.append(f"T3 ready: got {msg!r}")
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# T4: rx_pulse → "RX\r\n"
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ctx.set(dut.rx_pulse, 1)
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await ctx.tick()
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ctx.set(dut.rx_pulse, 0)
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msg = await recv_str(ctx, len(b"RX\r\n"))
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print(f"T4 rx: {msg!r}")
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if msg != b"RX\r\n":
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errors.append(f"T4 rx: got {msg!r}")
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# T5: tx_pulse → "TX\r\n"
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ctx.set(dut.tx_pulse, 1)
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await ctx.tick()
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ctx.set(dut.tx_pulse, 0)
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msg = await recv_str(ctx, len(b"TX\r\n"))
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print(f"T5 tx: {msg!r}")
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if msg != b"TX\r\n":
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errors.append(f"T5 tx: got {msg!r}")
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# T6: send 'r' → reinit pulse.
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# Poll tick-by-tick: the pulse fires ~100 cycles before send completes.
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got = await send_byte_watch(ctx, ord('r'), dut.reinit)
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print(f"T6 reinit after 'r': {got}")
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if not got:
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errors.append("T6 reinit: pulse not seen")
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# T7: send unknown byte → no reinit
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got = await send_byte_watch(ctx, ord('x'), dut.reinit)
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print(f"T7 reinit after 'x': {got} (want 0)")
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if got:
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errors.append("T7 spurious reinit on 'x'")
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sim = Simulator(dut)
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sim.add_clock(Period(MHz=24))
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sim.add_testbench(testbench)
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with sim.write_vcd("UARTConsole.vcd"):
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sim.run()
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if errors:
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print("\nFAILURES:")
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for e in errors:
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print(" ", e)
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sys.exit(1)
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else:
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print("\nAll UARTConsole tests passed.")
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