Added full design created with Claude
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Dennis Brentjes
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"""EEPROM model — exi domain.
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Emulates the MX98730EC's 93C46 serial EEPROM.
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93C46 protocol (Microwire, bit-bang)
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-------------------------------------
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CS=1 activates the device.
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Data clocked on rising SK edge, 9-bit header then data:
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Bit 0: start (always 1)
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Bit 1: opcode MSB } READ = 10
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Bit 2: opcode LSB }
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Bits 3–8: 6-bit address (MSB first)
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After the 9th rising SK the DO line presents the MSB of the 16-bit word.
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Each subsequent rising SK advances one bit (MSB→LSB).
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Shift register `shift_in` convention
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--------------------------------------
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`Cat(di_s, shift_in[:-1])` places di_s at bit 0 and shifts existing bits up.
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After N edges:
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shift_in[N-1] = first bit received (start)
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shift_in[0] = last bit received so far
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At bit_ctr==8 (after 8 edges, receiving 9th on di_s):
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shift_in[7] = start (bit 0)
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shift_in[6] = opcode MSB (bit 1)
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shift_in[5] = opcode LSB (bit 2)
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shift_in[4:0] = addr[5:1] (bits 3–7, MSB first→LSB first in register)
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di_s = addr[0] (bit 8)
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opcode = Cat(shift_in[5], shift_in[6]) → 0b10 = READ
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address = Cat(di_s, shift_in[0:5]) → addr[0..5]
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EEPROM content (64 × 16-bit words)
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-------------------------------------
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Words 0–2 hold the source MAC address (Nintendo OUI 00:09:BF:AA:BB:CC).
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The GC BBA driver reads words 0–3 then copies to PAR0–5.
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"""
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from amaranth import *
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from amaranth.lib.cdc import FFSynchronizer
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__all__ = ["EEPROMModel"]
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_EEPROM_WORDS = [
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0x0009, # word 0: PAR0=0x00, PAR1=0x09
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0xBFAA, # word 1: PAR2=0xBF, PAR3=0xAA
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0xBBCC, # word 2: PAR4=0xBB, PAR5=0xCC
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0x0000, # word 3: checksum placeholder
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]
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_EEPROM_WORDS += [0x0000] * (64 - len(_EEPROM_WORDS))
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_OP_READ = 0b10 # opcode for READ
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class EEPROMModel(Elaboratable):
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"""93C46 serial EEPROM model in the exi domain (read-only).
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Ports
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-----
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sk / cs / di : bit-bang inputs (raw async; synchronized internally)
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do : serial data output
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"""
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def __init__(self):
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self.sk = Signal()
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self.cs = Signal()
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self.di = Signal()
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self.do = Signal()
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def elaborate(self, platform):
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m = Module()
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words = Array([Signal(16, init=v, name=f"e{i}") for i, v in enumerate(_EEPROM_WORDS)])
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# ── Input synchronization (async → exi, 2 stages) ────────────────
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sk_s = Signal()
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cs_s = Signal()
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di_s = Signal()
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m.submodules.sync_sk = FFSynchronizer(self.sk, sk_s, o_domain="exi")
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m.submodules.sync_cs = FFSynchronizer(self.cs, cs_s, o_domain="exi")
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m.submodules.sync_di = FFSynchronizer(self.di, di_s, o_domain="exi")
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sk_prev = Signal()
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m.d.exi += sk_prev.eq(sk_s)
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rising_sk = Signal()
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m.d.comb += rising_sk.eq(sk_s & ~sk_prev)
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# ── State ─────────────────────────────────────────────────────────
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shift_in = Signal(9)
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bit_ctr = Signal(4) # 0..8 during header receive
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shift_out = Signal(16) # data word being shifted out MSB-first
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out_ctr = Signal(4) # 0..15, counts bits shifted out
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in_read = Signal() # 1 while outputting a word
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# DO is combinatorial: MSB of shift_out while in read-out phase
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m.d.comb += self.do.eq(Mux(in_read, shift_out[15], 0))
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with m.If(~cs_s):
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m.d.exi += bit_ctr.eq(0)
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m.d.exi += in_read.eq(0)
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m.d.exi += out_ctr.eq(0)
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with m.Elif(rising_sk):
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with m.If(in_read):
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# Shift out next bit (MSB first: left shift, zero into LSB)
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m.d.exi += shift_out.eq(Cat(0, shift_out[:-1]))
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with m.If(out_ctr == 15):
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m.d.exi += in_read.eq(0)
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m.d.exi += out_ctr.eq(0)
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with m.Else():
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m.d.exi += out_ctr.eq(out_ctr + 1)
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with m.Else():
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# Shift di_s in at bit 0 (existing bits move up)
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m.d.exi += shift_in.eq(Cat(di_s, shift_in[:-1]))
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m.d.exi += bit_ctr.eq(bit_ctr + 1)
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with m.If(bit_ctr == 8):
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# 9th bit (di_s = addr[0]) arrives.
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# shift_in[7] = start, [6]=op_MSB, [5]=op_LSB, [4:0]=addr[5:1]
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op = Cat(shift_in[5], shift_in[6]) # 0b10 for READ
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adr = Cat(di_s, shift_in[0:5]) # addr[0..5]
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with m.If(op == _OP_READ):
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m.d.exi += shift_out.eq(words[adr])
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m.d.exi += in_read.eq(1)
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m.d.exi += out_ctr.eq(0)
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return m
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# ── Testbench ─────────────────────────────────────────────────────────────
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if __name__ == "__main__":
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import sys
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from amaranth.sim import Simulator, Period
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dut = EEPROMModel()
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errors = []
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HALF = 6 # exi-domain ticks per SK half-period (much longer than sync latency)
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async def eeprom_read(ctx, addr):
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"""93C46 READ at 6-bit address; returns 16-bit word.
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DO is read BEFORE each rising SK edge, since in_read=1 causes
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shift_out[15] to be valid between edges. After 16 reads the full
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16-bit word is assembled MSB-first.
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"""
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ctx.set(dut.cs, 1)
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ctx.set(dut.sk, 0)
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await ctx.tick("exi").repeat(HALF)
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# Transmit 9 bits: start(1) + opcode READ(10) + addr[5:0] MSB-first
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bits = [1, 1, 0]
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for a in range(5, -1, -1):
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bits.append((addr >> a) & 1)
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for bit in bits:
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ctx.set(dut.di, bit)
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ctx.set(dut.sk, 1) # rising edge: DUT latches bit
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await ctx.tick("exi").repeat(HALF)
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ctx.set(dut.sk, 0)
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await ctx.tick("exi").repeat(HALF)
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# After 9th falling SK: in_read=1, shift_out=word[addr], do=MSB.
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# Read DO before each rising edge (it is valid in the LOW phase).
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result = 0
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for _ in range(16):
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result = (result << 1) | ctx.get(dut.do) # sample before rising SK
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ctx.set(dut.sk, 1)
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await ctx.tick("exi").repeat(HALF)
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ctx.set(dut.sk, 0)
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await ctx.tick("exi").repeat(HALF)
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ctx.set(dut.cs, 0)
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await ctx.tick("exi").repeat(HALF)
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return result
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async def testbench(ctx):
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await ctx.tick("exi").repeat(4)
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ctx.set(dut.cs, 0)
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ctx.set(dut.sk, 0)
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ctx.set(dut.di, 0)
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await ctx.tick("exi").repeat(4)
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w0 = await eeprom_read(ctx, 0)
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print(f"T1 word 0 = 0x{w0:04X} (expected 0x0009)")
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if w0 != 0x0009:
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errors.append(f"T1: word 0 = 0x{w0:04X}, expected 0x0009")
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w1 = await eeprom_read(ctx, 1)
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print(f"T2 word 1 = 0x{w1:04X} (expected 0xBFAA)")
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if w1 != 0xBFAA:
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errors.append(f"T2: word 1 = 0x{w1:04X}, expected 0xBFAA")
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w2 = await eeprom_read(ctx, 2)
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print(f"T3 word 2 = 0x{w2:04X} (expected 0xBBCC)")
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if w2 != 0xBBCC:
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errors.append(f"T3: word 2 = 0x{w2:04X}, expected 0xBBCC")
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# T4: word 3 → 0x0000
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w3 = await eeprom_read(ctx, 3)
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print(f"T4 word 3 = 0x{w3:04X} (expected 0x0000)")
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if w3 != 0x0000:
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errors.append(f"T4: word 3 = 0x{w3:04X}, expected 0x0000")
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sim = Simulator(dut)
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sim.add_clock(Period(MHz=24), domain="exi")
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sim.add_testbench(testbench)
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with sim.write_vcd("EEPROMModel.vcd"):
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sim.run()
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if errors:
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print("\nFAILURES:")
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for e in errors:
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print(" ", e)
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sys.exit(1)
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else:
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print("\nAll tests passed.")
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