Added full design created with Claude
This commit is contained in:
Dennis Brentjes
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"""SPRAM arbiter — sync domain (24 MHz).
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Owns the iCE40UP5K 128 KB SPRAM (SB_SPRAM256KA, 16-bit wide) and arbitrates
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between two clients:
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Client A (EXI read) : prefetch pipeline; low priority.
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Client B (ETH write): RXFrameAssembler; high priority.
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ETH writes win when both clients are active. This is safe because the GC only
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reads pages that the ETH engine has already finished writing (ring-buffer
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invariant).
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SPRAM addressing
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-----------------
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SB_SPRAM256KA is 64 K × 16-bit. Byte addressing:
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ADDRESS = byte_addr >> 1
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MASKWREN[3:0]:
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0b0011 → write lower byte (byte_addr even)
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0b1100 → write upper byte (byte_addr odd)
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Read: both bytes returned; pick the right one from DATAOUT based on addr bit 0.
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Read latency: 1 synchronous cycle — result of cycle N is valid at N+1.
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In simulation (platform is None) a behavioural Array model is used instead of
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the SB_SPRAM256KA Instance so tests run without IceStorm.
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"""
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from amaranth import *
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from amaranth.lib.memory import Memory
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__all__ = ["SPRAMArbiter"]
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_SPRAM_WORDS = 65536 # 64 K 16-bit words = 128 KB
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class SPRAMArbiter(Elaboratable):
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"""Arbitrated SPRAM controller in the sync domain.
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EXI read interface (from BBARegisterFile spram_req / spram_rsp FIFOs)
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----------------------------------------------------------------------
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exi_req_addr : 16-bit byte address to read
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exi_req_valid : FIFO r_rdy — a request is waiting
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exi_req_ready : FIFO r_en — pop the request (asserted when serviced)
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exi_rsp_data : 8-bit result byte
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exi_rsp_valid : FIFO w_en — push result when valid
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ETH write interface (from RXFrameAssembler)
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-------------------------------------------
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eth_wr_addr : 16-bit byte address to write
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eth_wr_data : 8-bit byte value
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eth_wr_valid : write request present
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eth_wr_ready : write accepted this cycle
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"""
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def __init__(self):
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# EXI read interface
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self.exi_req_addr = Signal(16)
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self.exi_req_valid = Signal()
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self.exi_req_ready = Signal()
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self.exi_rsp_data = Signal(8)
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self.exi_rsp_valid = Signal()
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# ETH write interface
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self.eth_wr_addr = Signal(16)
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self.eth_wr_data = Signal(8)
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self.eth_wr_valid = Signal()
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self.eth_wr_ready = Signal()
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def elaborate(self, platform):
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m = Module()
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# ── SPRAM instantiation (hardware vs simulation) ──────────────────
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spram_addr = Signal(14) # word address (byte_addr >> 1)
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spram_din = Signal(16)
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spram_dout = Signal(16)
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spram_wren = Signal()
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spram_mask = Signal(4) # MASKWREN
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if platform is None:
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# Behavioural model: synchronous read with 1-cycle latency.
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# Memory is a Component; read/write ports are obtained from it
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# and wired via its submodule ports (not added as separate submodules).
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mem = Memory(shape=16, depth=_SPRAM_WORDS, init=[])
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m.submodules.mem = mem
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mem_rd = mem.read_port(domain="sync", transparent_for=[])
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mem_wr = mem.write_port(domain="sync", granularity=8)
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# en[0] = lower byte enable, en[1] = upper byte enable
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byte0_en = Signal()
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byte1_en = Signal()
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m.d.comb += [
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byte0_en .eq(spram_wren & (spram_mask[0] | spram_mask[1])),
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byte1_en .eq(spram_wren & (spram_mask[2] | spram_mask[3])),
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mem_rd.addr .eq(spram_addr),
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mem_rd.en .eq(1),
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spram_dout .eq(mem_rd.data),
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mem_wr.addr .eq(spram_addr),
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mem_wr.data .eq(spram_din),
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mem_wr.en .eq(Cat(byte0_en, byte1_en)),
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]
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else:
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# Hardware: instantiate two SB_SPRAM256KA (64K×16 each; use one)
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m.submodules.spram = Instance(
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"SB_SPRAM256KA",
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i_ADDRESS = spram_addr,
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i_DATAIN = spram_din,
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i_MASKWREN = spram_mask,
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i_WREN = spram_wren,
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i_CHIPSELECT = Const(1, 1),
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i_CLOCK = ClockSignal("sync"),
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i_STANDBY = Const(0, 1),
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i_SLEEP = Const(0, 1),
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i_POWEROFF = Const(1, 1),
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o_DATAOUT = spram_dout,
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)
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# ── Arbiter pipeline ─────────────────────────────────────────────
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# Stage 1: issue SPRAM address and control signals (combinatorial)
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# Stage 2: capture SPRAM output into rsp_buf (synchronous, 1-cycle)
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read_pending = Signal() # a read address was issued last cycle
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read_was_odd = Signal() # byte address bit 0 of the pending read
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rsp_buf = Signal(8) # registered response byte; valid when exi_rsp_valid
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# Combinatorial defaults
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m.d.comb += [
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spram_wren .eq(0),
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spram_mask .eq(0),
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spram_din .eq(0),
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spram_addr .eq(0),
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self.exi_req_ready.eq(0),
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self.eth_wr_ready .eq(0),
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self.exi_rsp_data .eq(rsp_buf), # always sourced from registered buffer
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]
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# Registered defaults
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m.d.sync += [
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self.exi_rsp_valid.eq(0),
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read_pending .eq(0),
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]
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# ETH write has priority
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with m.If(self.eth_wr_valid):
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m.d.comb += [
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spram_addr .eq(self.eth_wr_addr[1:]),
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spram_wren .eq(1),
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self.eth_wr_ready.eq(1),
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]
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with m.If(self.eth_wr_addr[0]):
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m.d.comb += [
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spram_din [8:16].eq(self.eth_wr_data),
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spram_mask .eq(0b1100),
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]
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with m.Else():
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m.d.comb += [
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spram_din [0:8].eq(self.eth_wr_data),
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spram_mask .eq(0b0011),
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]
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# EXI read (lower priority)
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with m.Elif(self.exi_req_valid):
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m.d.comb += [
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spram_addr .eq(self.exi_req_addr[1:]),
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self.exi_req_ready.eq(1),
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]
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m.d.sync += [
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read_pending.eq(1),
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read_was_odd.eq(self.exi_req_addr[0]),
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]
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# Capture SPRAM output into registered buffer after 1-cycle latency
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with m.If(read_pending):
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with m.If(read_was_odd):
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m.d.sync += rsp_buf.eq(spram_dout[8:16])
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with m.Else():
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m.d.sync += rsp_buf.eq(spram_dout[0:8])
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m.d.sync += self.exi_rsp_valid.eq(1)
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return m
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# ── Testbench ─────────────────────────────────────────────────────────────
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if __name__ == "__main__":
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import sys
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from amaranth.sim import Simulator, Period
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dut = SPRAMArbiter()
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errors = []
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async def testbench(ctx):
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await ctx.tick("sync").repeat(2)
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# T1: ETH write to even byte address 0x0100, then EXI read it back
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ctx.set(dut.eth_wr_addr, 0x0100)
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ctx.set(dut.eth_wr_data, 0xAB)
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ctx.set(dut.eth_wr_valid, 1)
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await ctx.tick("sync").repeat(1)
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accepted = ctx.get(dut.eth_wr_ready)
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if not accepted:
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errors.append("T1 eth write not accepted")
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ctx.set(dut.eth_wr_valid, 0)
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await ctx.tick("sync").repeat(1)
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# Issue EXI read of the same address
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ctx.set(dut.exi_req_addr, 0x0100)
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ctx.set(dut.exi_req_valid, 1)
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await ctx.tick("sync").repeat(1) # clock A: read issued, read_pending=1
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ctx.set(dut.exi_req_valid, 0)
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await ctx.tick("sync").repeat(1) # clock B: SPRAM output captured, valid=1
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# Check HERE — exi_rsp_valid is 1 for exactly this one cycle
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rdata = ctx.get(dut.exi_rsp_data)
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rvalid = ctx.get(dut.exi_rsp_valid)
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if rdata != 0xAB:
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errors.append(f"T1 read back: expected 0xAB, got 0x{rdata:02X}")
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if not rvalid:
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errors.append("T1 exi_rsp_valid not set")
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print(f"T1 even addr read-back: data=0x{rdata:02X} valid={rvalid}")
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await ctx.tick("sync").repeat(2)
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# T2: ETH write to ODD byte address 0x0101, read back
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ctx.set(dut.eth_wr_addr, 0x0101)
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ctx.set(dut.eth_wr_data, 0xCD)
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ctx.set(dut.eth_wr_valid, 1)
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await ctx.tick("sync").repeat(1)
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ctx.set(dut.eth_wr_valid, 0)
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await ctx.tick("sync").repeat(1)
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ctx.set(dut.exi_req_addr, 0x0101)
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ctx.set(dut.exi_req_valid, 1)
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await ctx.tick("sync").repeat(1)
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ctx.set(dut.exi_req_valid, 0)
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await ctx.tick("sync").repeat(1)
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rdata = ctx.get(dut.exi_rsp_data)
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if rdata != 0xCD:
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errors.append(f"T2 odd addr read-back: expected 0xCD, got 0x{rdata:02X}")
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print(f"T2 odd addr read-back: data=0x{rdata:02X}")
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await ctx.tick("sync").repeat(2)
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# T3: ETH write wins when both clients active simultaneously
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# Write 0xEE to 0x0200
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ctx.set(dut.eth_wr_addr, 0x0200)
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ctx.set(dut.eth_wr_data, 0xEE)
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ctx.set(dut.eth_wr_valid, 1)
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ctx.set(dut.exi_req_addr, 0x0100) # also wants to read
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ctx.set(dut.exi_req_valid, 1)
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await ctx.tick("sync").repeat(1)
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eth_won = ctx.get(dut.eth_wr_ready)
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exi_blocked = not ctx.get(dut.exi_req_ready)
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ctx.set(dut.eth_wr_valid, 0)
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ctx.set(dut.exi_req_valid, 0)
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if not eth_won:
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errors.append("T3 ETH priority: ETH write not accepted")
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if not exi_blocked:
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errors.append("T3 ETH priority: EXI read was not blocked")
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print(f"T3 ETH priority: eth_won={eth_won} exi_blocked={exi_blocked}")
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sim = Simulator(dut)
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sim.add_clock(Period(MHz=24), domain="sync")
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sim.add_testbench(testbench)
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with sim.write_vcd("SPRAMArbiter.vcd"):
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sim.run()
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if errors:
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print("\nFAILURES:")
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for e in errors:
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print(" ", e)
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sys.exit(1)
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else:
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print("\nAll tests passed.")
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