Added full design created with Claude
This commit is contained in:
Dennis Brentjes
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"""TX frame drain — sync domain (24 MHz).
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Drains the tx_bytes AsyncFIFO (written by BBARegisterFile in the exi domain),
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forwards each byte to W5500SPIMaster with SOF/EOF framing, then pulses tx_irq
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to notify the GC that the transmit is complete.
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Flow
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----
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1. Wait for tx_len FIFO to have a length word (signals a complete frame queued).
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2. Pop the length from tx_len FIFO.
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3. Assert tx_sof on first byte, tx_eof on last byte, consuming tx_bytes FIFO.
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4. When W5500SPIMaster accepts the final byte: pulse tx_irq.
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The tx_bytes AsyncFIFO (exi→sync, 8-bit, depth=16) and tx_ctrl FIFO (exi→sync,
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16-bit, depth=4) are instantiated in BBARegisterFile and their sync-domain read
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sides are exposed as ports wired here by BBATop.
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"""
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from amaranth import *
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__all__ = ["TXFrameDrain"]
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class TXFrameDrain(Elaboratable):
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"""Drains BBA TX FIFOs and forwards frames to W5500SPIMaster.
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TX FIFO read interfaces (async FIFOs, sync-domain read side)
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---------------------------------------------------------------
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tx_bytes_r_data / tx_bytes_r_en / tx_bytes_r_rdy : byte stream
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tx_ctrl_r_data / tx_ctrl_r_en / tx_ctrl_r_rdy : 16-bit frame length
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W5500 streaming output (sync domain, to W5500SPIMaster)
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-------------------------------------------------------
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tx_data / tx_valid / tx_ready / tx_sof / tx_eof
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CDC output (sync→exi, via PulseSynchronizer in BBATop)
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-------------------------------------------------------
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tx_irq : 1-cycle pulse when frame transmission is handed off to W5500SPIMaster
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"""
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def __init__(self):
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# tx_bytes FIFO read side
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self.tx_bytes_r_data = Signal(8)
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self.tx_bytes_r_en = Signal()
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self.tx_bytes_r_rdy = Signal()
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# tx_ctrl FIFO read side (frame length)
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self.tx_ctrl_r_data = Signal(16)
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self.tx_ctrl_r_en = Signal()
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self.tx_ctrl_r_rdy = Signal()
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# W5500 streaming TX interface
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self.tx_data = Signal(8)
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self.tx_valid = Signal()
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self.tx_ready = Signal()
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self.tx_sof = Signal()
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self.tx_eof = Signal()
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# TX done pulse → PulseSynchronizer
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self.tx_irq = Signal()
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def elaborate(self, platform):
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m = Module()
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frame_len = Signal(16) # bytes still to LOAD from FIFO (incl. held one)
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is_first = Signal() # next byte loaded is the first (SOF)
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load_pending = Signal() # 1-bit "more bytes to load" flag (replaces
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# a 16-bit frame_len!=0 compare in the
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# combinational FIFO read-enable path)
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# ── Registered holding stage presented to W5500 ──────────────────
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# All W5500-facing outputs are driven from these registers. This
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# breaks the long combinational path that previously ran from the
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# tx_bytes FIFO read pointer, out through W5500 (tx_ready) and the
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# is_first/eof logic, and back into the FIFO pointer increment — the
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# sync-domain critical path. The FIFO read-enable now depends only on
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# the registered hold_valid and the FIFO's own r_rdy.
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hold_data = Signal(8)
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hold_valid = Signal()
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hold_sof = Signal()
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hold_eof = Signal()
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m.d.sync += self.tx_irq.eq(0) # default
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m.d.comb += [
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self.tx_data .eq(hold_data),
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self.tx_valid.eq(hold_valid),
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self.tx_sof .eq(hold_sof),
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self.tx_eof .eq(hold_eof),
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]
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# W5500 took the currently-held byte this cycle
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hold_consumed = Signal()
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m.d.comb += hold_consumed.eq(hold_valid & self.tx_ready)
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# FIFO read-enable defaults (combinational, no W5500 dependency)
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m.d.comb += self.tx_bytes_r_en.eq(0)
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m.d.comb += self.tx_ctrl_r_en .eq(0)
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with m.FSM(domain="sync", name="tx_fsm"):
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with m.State("IDLE"):
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# Wait for a complete frame length in tx_ctrl FIFO
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with m.If(self.tx_ctrl_r_rdy):
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m.d.comb += self.tx_ctrl_r_en.eq(1)
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m.d.sync += frame_len.eq(self.tx_ctrl_r_data)
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m.d.sync += is_first.eq(1)
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# A frame with length 0 has nothing to load.
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m.d.sync += load_pending.eq(self.tx_ctrl_r_data != 0)
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m.next = "DRAIN"
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with m.State("DRAIN"):
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# Load the next byte into the holding register only when it is
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# empty. Costs one idle sync cycle per byte, negligible
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# against the W5500 SPI rate (~16 sync cycles/byte), and keeps
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# tx_ready off the FIFO read-enable path entirely.
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#
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# The gate uses the registered 1-bit load_pending instead of a
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# 16-bit (frame_len != 0) reduction, so the combinational path
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# consume_r_gry → r_rdy → do_load → tx_bytes_r_en stays shallow.
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do_load = Signal()
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m.d.comb += do_load.eq(
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~hold_valid & self.tx_bytes_r_rdy & load_pending
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)
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m.d.comb += self.tx_bytes_r_en.eq(do_load)
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with m.If(hold_consumed):
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m.d.sync += hold_valid.eq(0)
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with m.If(hold_eof):
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m.d.sync += self.tx_irq.eq(1)
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m.next = "IDLE"
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with m.If(do_load):
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m.d.sync += hold_data .eq(self.tx_bytes_r_data)
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m.d.sync += hold_valid.eq(1)
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m.d.sync += hold_sof .eq(is_first)
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m.d.sync += hold_eof .eq(frame_len == 1)
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m.d.sync += is_first .eq(0)
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m.d.sync += frame_len .eq(frame_len - 1)
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# Last byte just loaded → stop further loads (registered).
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with m.If(frame_len == 1):
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m.d.sync += load_pending.eq(0)
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return m
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# ── Testbench ─────────────────────────────────────────────────────────────
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if __name__ == "__main__":
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import sys
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from amaranth.sim import Simulator, Period
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dut = TXFrameDrain()
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errors = []
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async def _send_frame(ctx, frame):
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"""Drive one frame through the TXFrameDrain DUT.
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Returns (received_bytes, seen_sof, seen_eof, saw_irq).
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Key timing: tx_sof/tx_eof are combinatorial outputs that depend on
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registered signals (is_first, frame_len) BEFORE they update. We read
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them BEFORE each tick to capture the correct values, then advance the
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FIFO AFTER the tick.
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"""
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ctx.set(dut.tx_ctrl_r_data, len(frame))
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ctx.set(dut.tx_ctrl_r_rdy, 1)
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ctx.set(dut.tx_bytes_r_data, frame[0])
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ctx.set(dut.tx_bytes_r_rdy, 1)
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# Tick 0: IDLE pops ctrl word (comb), FSM→DRAIN, frame_len registered
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await ctx.tick("sync").repeat(1)
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# Deassert ctrl FIFO so FSM doesn't re-pop when it returns to IDLE
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ctx.set(dut.tx_ctrl_r_rdy, 0)
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received = []
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seen_sof = False
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seen_eof = False
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saw_irq = False
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for _ in range(len(frame) + 10):
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# Read comb signals BEFORE the tick (is_first and frame_len still
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# reflect pre-tick registered values, so sof/eof are correct)
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if ctx.get(dut.tx_valid):
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d = ctx.get(dut.tx_data)
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sof = ctx.get(dut.tx_sof)
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eof = ctx.get(dut.tx_eof)
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received.append(d)
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seen_sof = seen_sof or sof
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seen_eof = seen_eof or eof
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await ctx.tick("sync").repeat(1)
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if ctx.get(dut.tx_irq):
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saw_irq = True
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break
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# Advance FIFO AFTER the tick: present next byte for next tick
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if len(received) < len(frame):
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ctx.set(dut.tx_bytes_r_data, frame[len(received)])
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elif len(received) == len(frame):
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ctx.set(dut.tx_bytes_r_rdy, 0)
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return received, seen_sof, seen_eof, saw_irq
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async def testbench(ctx):
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await ctx.tick("sync").repeat(2)
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ctx.set(dut.tx_ready, 1)
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# ── T1: 4-byte frame ─────────────────────────────────────────────────
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frame = [0xDE, 0xAD, 0xBE, 0xEF]
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received, seen_sof, seen_eof, saw_irq = await _send_frame(ctx, frame)
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print(f"T1 received={[hex(b) for b in received]} sof={seen_sof} eof={seen_eof} tx_irq={saw_irq}")
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if received != frame:
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errors.append(f"T1 bytes mismatch: got {received}, want {frame}")
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if not seen_sof:
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errors.append("T1: SOF never seen")
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if not seen_eof:
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errors.append("T1: EOF never seen")
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if not saw_irq:
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errors.append("T1: tx_irq never pulsed")
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await ctx.tick("sync").repeat(4)
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# ── T2: Single-byte frame — SOF and EOF on same byte ─────────────────
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frame2 = [0x42]
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received2, s2_sof, s2_eof, s2_irq = await _send_frame(ctx, frame2)
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print(f"T2 byte=0x{received2[0] if received2 else 0:02X} sof={s2_sof} eof={s2_eof} tx_irq={s2_irq}")
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if received2 != frame2:
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errors.append(f"T2: bytes wrong, got {received2}")
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if not (s2_sof and s2_eof):
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errors.append("T2: SOF+EOF both must be set for 1-byte frame")
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if not s2_irq:
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errors.append("T2: tx_irq not seen for 1-byte frame")
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sim = Simulator(dut)
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sim.add_clock(Period(MHz=24), domain="sync")
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sim.add_testbench(testbench)
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with sim.write_vcd("TXFrameDrain.vcd"):
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sim.run()
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if errors:
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print("\nFAILURES:")
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for e in errors:
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print(" ", e)
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sys.exit(1)
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else:
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print("\nAll tests passed.")
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