Clock the EXI bit engine from the EXI pin: timing closes on all 8 seeds
Replaces the PLL-fed 54 MHz `capture` domain, which oversampled the GC's
27 MHz EXI clock 2x and so put BIT-level timing across a CDC boundary: the
engine's view of the clock lagged the pin by 2 FFSynchronizer stages plus a
register (~55 ns) against a 37 ns bit time, so MISO came out ~2 bits late and
the GC read 0x17 as 05 C0. No amount of oversampling fixes that -- 54 MHz
gives only 2 ticks per bit and the part cannot close the 81 MHz that 3x needs.
The engine is now clocked by the pin itself (pin 44 = global buffer input net
6, no board change), making MISO clock-to-Q. ExiCapture creates four domains:
exiclk (posedge, samples MOSI), exiclk_n (negedge, drives MISO), both
async-reset by CS, plus reset-less exififo_w/exififo_r for the byte FIFO sides
-- reset-less because resetting one side of an AsyncFIFO desynchronises its
gray pointers, and posedge because AsyncFIFO has a posedge-only reset CDC
internally and cannot host a negedge side.
Also removes the SPRAM response FIFO. The DMA read was one byte late because
the round trip did not fit the protocol's turnaround byte; the arbiter already
exposed valid/ready, so the FIFO bought a cycle of latency and nothing else.
The response is handled outside the FSM (the reply lands in RHDR_PAD, not
SPRAM_STREAM) with a one-entry hold for when tx_fifo is momentarily full.
The PLL was left instantiated but unused after the rewrite; removing it frees
the hard macro and pin 35 (which stays unconnected only because the board is
already built that way). This is what lifted the pass rate:
domain target before after
clk (sync) 24 MHz 28.1-30.2 26.4-32.2 8/8
capture_clk 54 MHz 2 of 8 PASS (gone)
EXI pin domain 27 MHz -- 45.6-64.4 8/8
Best seed 3: clk 32.18 MHz, EXI 55.86 MHz. The binding constraint has FLIPPED
-- `clk` (1.10-1.34x) is now tighter than the EXI domain (1.69-2.39x) -- so
synth.py ranks seeds by worst RELATIVE margin, not by the EXI number.
synth.py could not have scored this design at all: it required the vanished
capture_clk, and its regex '(\w+)' cannot match nextpnr's exi_clk_$glb_clk
(no $ in \w). add_clock_constraint was also landing on the wrong net -- under
EXI_J4 the clock is the AND of two pads, not either pad -- so nextpnr silently
fell back to a 12 MHz default and under-optimised the whole EXI domain.
Testbenches:
- spi_mode3_slave had lost its testbench entirely in the rewrite. Restored
with a strict Mode 3 master (changes MOSI on the falling edge, samples MISO
in the clock-low phase) and MUTATION-TESTED: flipping either clock edge in
the RTL makes it fail. Both of those bugs previously reached silicon
against a lax master that parked MOSI well before the edge.
- exi_j4 T2/T3 returned [0,4,2,2]. Real bug: the engine latches the FIFO head
at each byte boundary, so a 2-byte command header leaves only ONE drain
slot. DEVID streamed zeros until CS and left two stale bytes -- one too
many -- so the NEXT enumeration came back a slot late. DEVID now pushes
exactly four bytes and stops. Register-space reads may still over-push:
their 4-byte header gives three drain slots.
- Dead ports removed from SPIMode3Slave (hdr_bytes, frame_start, cs_active,
byte_idx) and the mode2 parameter is gone -- there is one correct edge
convention and it is now enforced by tests.
All 14 module suites pass, plus bba_top at EXI_HALF=1/2/8.
CLAUDE.md: rewrote the clocking, CDC inventory and module tables; marked the
2026-09-30 capture_clk measurements historical; and corrected the line in
"Critical Protocol Notes" that still stated the INVERTED edge convention
("MOSI sampled on falling, MISO driven on rising" is Mode 2) -- the original
implementation followed that doc error.
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
This commit is contained in:
+137
-17
@@ -53,10 +53,10 @@ class SPIMode3Slave(Elaboratable):
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rx_byte : last complete received byte (valid while rx_valid is high)
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rx_valid : 1-cycle pulse in `exiclk` when rx_byte holds a new byte
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tx_byte : byte to transmit; sampled at each byte boundary
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tx_load : 1-cycle pulse in `exiclk_n` asking upstream for the next byte
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hdr_bytes : how many leading bytes are header (MISO don't-care). Pops are
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suppressed until past them, so the first response byte the register
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file pushes lands in data slot 0 rather than being eaten by the header.
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tx_load : 1-cycle pulse asking upstream for the next byte, one per byte
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boundary. No header-length or slot-threshold logic: see the TX comment
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in elaborate() for why unconditional pops are both sufficient and
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necessary.
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"""
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def __init__(self):
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@@ -71,29 +71,16 @@ class SPIMode3Slave(Elaboratable):
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self.tx_byte = Signal(8)
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self.tx_load = Signal()
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# Header length for this transaction, in bytes. The real protocol has
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# two forms selected by bit 7 of byte 0 (see docs/exi_protocol_real.md):
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# register space = 4-byte header, command space = 2-byte.
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self.hdr_bytes = Signal(3, init=4)
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# Transaction framing, generated in the slow domain by the parent.
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self.frame_start = Signal()
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self.cs_active = Signal()
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def elaborate(self, platform):
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m = Module()
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# ── RX: sample MOSI on the RISING edge (Mode 3 samples on edge 2) ──
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rx_shift = Signal(8)
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rx_bit = Signal(3)
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byte_idx = Signal(3, init=0) # bytes seen this transaction (saturating)
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nxt = Cat(self.spi_mosi, rx_shift[:-1]) # MSB-first: shift left, new bit at LSB
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m.d.exiclk += rx_shift.eq(nxt)
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m.d.exiclk += rx_bit.eq(rx_bit + 1)
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with m.If(rx_bit == 7):
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with m.If(byte_idx != 7):
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m.d.exiclk += byte_idx.eq(byte_idx + 1)
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# rx_byte/rx_valid are COMBINATIONAL, not registered. The clock stops
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# and CS rises immediately after a transaction's final bit, so a
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@@ -138,3 +125,136 @@ class SPIMode3Slave(Elaboratable):
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m.d.comb += self.spi_miso.eq(Mux(self.spi_cs_n, 1, tx_shift[7]))
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return m
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# ── Testbench ─────────────────────────────────────────────────────────────
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class _Harness(Elaboratable):
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"""Wraps the slave with the two pin-driven domains its parent normally
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creates, so the engine can be exercised standalone."""
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def __init__(self):
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self.dut = SPIMode3Slave()
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def elaborate(self, platform):
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m = Module()
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m.domains.exiclk = cd_p = ClockDomain(async_reset=True)
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m.domains.exiclk_n = cd_n = ClockDomain(async_reset=True,
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clk_edge="neg")
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d = self.dut
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m.d.comb += [
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cd_p.clk.eq(d.spi_clk), cd_p.rst.eq(d.spi_cs_n),
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cd_n.clk.eq(d.spi_clk), cd_n.rst.eq(d.spi_cs_n),
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]
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m.submodules.dut = d
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return m
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if __name__ == "__main__":
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import sys
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from amaranth.sim import Simulator, Period
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HP = Period(MHz=27) / 2 # one EXI half-period at the hardware rate
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top = _Harness()
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dut = top.dut
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failures = []
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def check(name, got, want):
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ok = got == want
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print(f" {'ok ' if ok else 'FAIL'} {name}: got {got}, want {want}")
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if not ok:
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failures.append(name)
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# A STRICT Mode 3 master. Unlike a convenience model that parks MOSI long
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# before the edge, this one changes MOSI exactly ON the falling edge and
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# samples MISO in the CLK-low phase. That is what makes the edge
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# convention observable: a slave that sampled MOSI on the falling edge
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# would capture the previous bit, and one that drove MISO on the rising
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# edge would come out a bit late. Both bugs shipped to hardware against a
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# lax master that could not see them.
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async def spi_byte(ctx, mosi_val, probe_rx=False):
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miso = 0
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rx = None
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for bit in range(7, -1, -1):
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ctx.set(dut.spi_clk, 0) # falling edge
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ctx.set(dut.spi_mosi, (mosi_val >> bit) & 1)
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await ctx.delay(HP)
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miso = (miso << 1) | ctx.get(dut.spi_miso) # sample in CLK-low
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if probe_rx and bit == 0:
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rx = (ctx.get(dut.rx_valid), ctx.get(dut.rx_byte))
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ctx.set(dut.spi_clk, 1) # rising edge: slave samples
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await ctx.delay(HP)
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return (miso, rx) if probe_rx else miso
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async def cs_low(ctx):
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ctx.set(dut.spi_clk, 1)
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ctx.set(dut.spi_cs_n, 0)
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await ctx.delay(HP)
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async def cs_high(ctx):
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ctx.set(dut.spi_clk, 1)
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await ctx.delay(HP)
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ctx.set(dut.spi_cs_n, 1)
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await ctx.delay(HP * 4)
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async def tb(ctx):
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ctx.set(dut.spi_cs_n, 1)
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ctx.set(dut.spi_clk, 1)
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ctx.set(dut.tx_byte, 0)
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await ctx.delay(HP * 4)
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# T1 — RX samples MOSI on the RISING edge, MSB first.
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# rx_byte/rx_valid are combinational and peak during the final bit,
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# which is the instant the parent's FIFO captures them.
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await cs_low(ctx)
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seen = []
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for b in (0x80, 0x00, 0x31, 0x00):
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_, (valid, byte) = await spi_byte(ctx, b, probe_rx=True)
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seen.append((valid, byte))
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await cs_high(ctx)
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check("T1 rx bytes", [b for _, b in seen], [0x80, 0x00, 0x31, 0x00])
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check("T1 rx_valid", [v for v, _ in seen], [1, 1, 1, 1])
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# T2 — TX: the byte latched at the end of slot N appears in slot N+1,
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# MSB first. Slot 0 is the reset value, before any load.
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await cs_low(ctx)
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ctx.set(dut.tx_byte, 0xA5)
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s0 = await spi_byte(ctx, 0x00)
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ctx.set(dut.tx_byte, 0x3C)
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s1 = await spi_byte(ctx, 0x00)
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ctx.set(dut.tx_byte, 0x00)
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s2 = await spi_byte(ctx, 0x00)
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await cs_high(ctx)
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check("T2 miso slot0 (pre-load)", hex(s0), hex(0x00))
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check("T2 miso slot1", hex(s1), hex(0xA5))
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check("T2 miso slot2", hex(s2), hex(0x3C))
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# T3 — tx_load pulses exactly once per byte, during the final bit.
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await cs_low(ctx)
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loads = 0
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for _ in range(3):
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for bit in range(8):
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ctx.set(dut.spi_clk, 0)
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await ctx.delay(HP)
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loads += ctx.get(dut.tx_load)
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ctx.set(dut.spi_clk, 1)
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await ctx.delay(HP)
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await cs_high(ctx)
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check("T3 tx_load pulses", loads, 3)
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# T4 — MISO releases HIGH when CS is deasserted, so it never fights
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# another EXI device sharing the bus.
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check("T4 miso idles high", ctx.get(dut.spi_miso), 1)
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sim = Simulator(top)
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sim.add_testbench(tb)
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with sim.write_vcd("SPIMode3Slave.vcd"):
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sim.run()
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if failures:
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print("\nFAILURES:")
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for f in failures:
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print(" -", f)
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sys.exit(1)
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print("\nAll tests passed.")
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