fix(w5100): unlock NETLCKR before writing GWR/SUBR/SHAR/SIPR (W5100S)
Second W5100S-vs-W5100 gotcha found at bring-up: the W5100S has a Network Lock Register (NETLCKR, 0x0071) the original W5100 lacks. It defaults to 0x00 (locked), and while locked, ALL writes to GWR/SUBR/SHAR/SIPR are silently dropped -- so the chip has no source IP/MAC and the UDP/MACRAW send builds nothing (chip reports SEND_OK but transmits nothing; socket registers aren't locked, which is why an indirect write/readback of Sn_PORT succeeded). Fix: write the unlock value 0x3A to NETLCKR right after MR enables indirect mode, before the network-config writes. On the bench this flipped the board from silent to actually keying frames onto the wire (magjack activity LED now blinks). Also: - bba_top.py test model: RX buffer base 0x6000 -> 0xC000 to match the W5100S buffer-base fix (the model hardcoded the old W5100 address). - w5100_selftest.py: added an indirect-mode (IDM) write/readback probe of a socket register + IND= field in the UART report, to isolate direct-vs-indirect access (confirmed indirect works on the real chip). Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
This commit is contained in:
+87
-29
@@ -91,6 +91,7 @@ class W5100SelfTest(Elaboratable):
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self.done = Signal() # high once the test has a verdict
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self.mr_ok = Signal() # MR reset self-cleared (chip alive)
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self.bad_bits = Signal(8) # data lines that failed read-back
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self.ind_ok = Signal() # indirect-mode (IDM) write/readback OK
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def elaborate(self, platform):
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m = Module()
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@@ -213,15 +214,58 @@ class W5100SelfTest(Elaboratable):
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with m.If(bus_done):
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with m.If(~bus_rd[7]):
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m.d.sync += mr_ok.eq(1)
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m.next = "REPORT"
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m.next = "IND_MODE"
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with m.Else():
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m.d.sync += ctr.eq(ctr + 1)
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with m.If(ctr == self._poll - 1):
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m.d.sync += mr_ok.eq(0) # never cleared
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m.next = "REPORT"
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m.next = "IND_MODE"
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with m.Else():
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m.next = "MR_POLL_ISSUE"
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# ── INDIRECT-mode probe: write+readback Sn_PORT of socket 3
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# (0x0704) through IDM_AR/IDM_DR, the exact access path the BBA
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# master uses to reach socket/buffer space. Direct mode (the walk
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# above) can only touch 0x0000-0x0003; this proves the chip honours
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# the indirect interface for the high address space too.
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with m.State("IND_MODE"): # enter indirect bus mode
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bus_write(_A_MR, _MR_IND)
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m.next = "IND_MODE_W"
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with m.State("IND_MODE_W"):
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with m.If(bus_done): m.next = "IND_WAR0"
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with m.State("IND_WAR0"):
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bus_write(_A_AR0, 0x07)
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m.next = "IND_WAR0_W"
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with m.State("IND_WAR0_W"):
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with m.If(bus_done): m.next = "IND_WAR1"
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with m.State("IND_WAR1"):
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bus_write(_A_AR1, 0x04)
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m.next = "IND_WAR1_W"
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with m.State("IND_WAR1_W"):
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with m.If(bus_done): m.next = "IND_WDR"
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with m.State("IND_WDR"):
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bus_write(_A_DR, 0xA5) # write pattern to Sn_PORT
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m.next = "IND_WDR_W"
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with m.State("IND_WDR_W"):
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with m.If(bus_done): m.next = "IND_RAR0"
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with m.State("IND_RAR0"):
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bus_write(_A_AR0, 0x07) # re-point AR (no auto-inc)
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m.next = "IND_RAR0_W"
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with m.State("IND_RAR0_W"):
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with m.If(bus_done): m.next = "IND_RAR1"
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with m.State("IND_RAR1"):
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bus_write(_A_AR1, 0x04)
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m.next = "IND_RAR1_W"
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with m.State("IND_RAR1_W"):
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with m.If(bus_done): m.next = "IND_RDR"
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with m.State("IND_RDR"):
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bus_read(_A_DR)
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m.next = "IND_RDR_W"
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with m.State("IND_RDR_W"):
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with m.If(bus_done):
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m.d.sync += self.ind_ok.eq(bus_rd == 0xA5)
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m.next = "REPORT"
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with m.State("REPORT"):
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m.d.comb += self.done.eq(1)
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@@ -273,7 +317,7 @@ class W5100SelfTest(Elaboratable):
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# ── UART status report (115200 8N1) ──────────────────────────────────
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# Continuously transmits "W5100 MROK=X BAD=YY <verdict>\r\n" once `done`.
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DIV = round(24_000_000 / 115_200) # 208 cycles / bit
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tmpl = list(b"W5100 MROK=0 BAD=00 ....\r\n") # X@11, hi@17, lo@18, verdict@20..23
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tmpl = list(b"W5100 MROK=0 BAD=00 IND=0 ....\r\n") # X@11 hi@17 lo@18 ind@24 verdict@26..29
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MSGLEN = len(tmpl)
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rom = Array([Const(b, 8) for b in tmpl])
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@@ -298,8 +342,9 @@ class W5100SelfTest(Elaboratable):
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with m.Case(11): m.d.comb += cur.eq(0x30 + mr_ok)
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with m.Case(17): m.d.comb += cur.eq(hexch(bad[4:8]))
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with m.Case(18): m.d.comb += cur.eq(hexch(bad[0:4]))
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with m.Case(24): m.d.comb += cur.eq(0x30 + self.ind_ok)
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for k in range(4):
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with m.Case(20 + k): m.d.comb += cur.eq(verd[8*k:8*k+8])
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with m.Case(26 + k): m.d.comb += cur.eq(verd[8*k:8*k+8])
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shift = Signal(10, init=0x3FF)
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nbits = Signal(range(11))
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@@ -395,32 +440,45 @@ if __name__ == "__main__":
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sim.add_clock(Period(MHz=24), domain="sync")
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async def w5100_model(ctx):
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mem = {} # direct-mode regs by A[1:0]
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for _ in range(8000):
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mem = {} # direct A (0-3) or ('i',addr)
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ar = 0; ind = False # IDM pointer, MR.IND state
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for _ in range(14000):
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await ctx.tick("sync")
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cs = ctx.get(dut.cs_n); rd = ctx.get(dut.rd_n); wr = ctx.get(dut.wr_n)
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a = ctx.get(dut.bus_addr); dko = ctx.get(dut.bus_data_o)
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if cs == 0 and wr == 0: # write strobe (idempotent)
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mem[a] = dko
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if cs == 0 and wr == 0: # write (idempotent)
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if bus_dead:
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pass
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elif a == _A_MR:
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mem[0] = dko; ind = bool(dko & _MR_IND)
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elif ind: # indirect: IDM_AR / IDM_DR
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if a == _A_AR0: ar = (ar & 0x00FF) | (dko << 8)
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elif a == _A_AR1: ar = (ar & 0xFF00) | dko
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elif a == _A_DR: mem[('i', ar)] = dko
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else: # direct: A[1:0] register
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mem[a] = dko
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if cs == 0 and rd == 0: # drive read data
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if bus_dead:
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ctx.set(dut.bus_data_i, 0xFF) # nothing drives -> float hi
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val = 0xFF
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elif a == _A_MR:
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mr = mem.get(_A_MR, 0) # reset self-clears only if
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ctx.set(dut.bus_data_i, # the clock is alive
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mr if clock_dead else (mr & 0x7F))
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else: # GAR0.. scratch R/W
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mr = mem.get(0, 0)
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val = mr if clock_dead else (mr & 0x7F) # reset self-clear
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elif ind and a == _A_DR:
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val = mem.get(('i', ar), 0)
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elif not ind:
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val = mem.get(a, 0)
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if break_bit is not None: # stuck-low data line
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val &= ~(1 << break_bit) & 0xFF
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ctx.set(dut.bus_data_i, val)
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else:
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val = 0
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if break_bit is not None and a != _A_MR: # stuck-low data line
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val &= ~(1 << break_bit) & 0xFF
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ctx.set(dut.bus_data_i, val)
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async def checker(ctx):
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for _ in range(4000):
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for _ in range(9000):
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await ctx.tick("sync")
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if ctx.get(dut.done):
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return (ctx.get(dut.mr_ok), ctx.get(dut.bad_bits))
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return (None, None)
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return (ctx.get(dut.mr_ok), ctx.get(dut.bad_bits), ctx.get(dut.ind_ok))
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return (None, None, None)
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result = {}
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async def tb(ctx):
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@@ -431,21 +489,21 @@ if __name__ == "__main__":
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return result["v"]
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ok = True
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mr, bad = run()
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print(f"[healthy] mr_ok={mr} bad={bad:#04x} -> GREEN solid")
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ok &= (mr == 1 and bad == 0)
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mr, bad, ind = run()
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print(f"[healthy] mr_ok={mr} bad={bad:#04x} ind_ok={ind} -> GREEN solid")
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ok &= (mr == 1 and bad == 0 and ind == 1)
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mr, bad = run(break_bit=3)
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print(f"[D3 broken] mr_ok={mr} bad={bad:#04x} -> green dark, RED 4 blinks")
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mr, bad, ind = run(break_bit=3)
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print(f"[D3 broken] mr_ok={mr} bad={bad:#04x} ind_ok={ind} -> green dark, RED 4 blinks")
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ok &= ((bad & 0x08) and bad != 0xFF)
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mr, bad = run(clock_dead=True)
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print(f"[clock/Y2 dead] mr_ok={mr} bad={bad:#04x} -> GREEN+RED slow together")
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mr, bad, ind = run(clock_dead=True)
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print(f"[clock/Y2 dead] mr_ok={mr} bad={bad:#04x} ind_ok={ind} -> GREEN+RED slow together")
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ok &= (mr == 0 and bad == 0)
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mr, bad = run(bus_dead=True)
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print(f"[unpowered/dead] mr_ok={mr} bad={bad:#04x} -> green dark, RED fast")
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ok &= (bad == 0xFF)
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mr, bad, ind = run(bus_dead=True)
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print(f"[unpowered/dead] mr_ok={mr} bad={bad:#04x} ind_ok={ind} -> green dark, RED fast")
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ok &= (bad == 0xFF and ind == 0)
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print("PASS" if ok else "FAIL")
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import sys; sys.exit(0 if ok else 1)
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