Adds last Todo item, fixes CPL and rotations.
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@@ -35,8 +35,8 @@ running list — items are **not** being worked yet, just recorded.
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D6/D8/D9/D12 = **C2980185** (24-21/G6C), amber D13 = **C424133** (24-21UYC).
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All Vf ≈ 2.0 V (3.3 V-rail + SB_RGBA_DRV safe), moderate mcd. New footprint
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`hardware/LED_1206_ReverseMount_Everlight_24-21.kicad_mod` (pad1=cathode,
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ø1.5 mm Edge.Cuts light-window). **⚠️ VERIFY the land + light-window aperture
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against the 24-21 datasheet during PCB layout** (footprint is a starting point).
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**ø1.7 mm Edge.Cuts light-window — datasheet-confirmed** 2026-08-28, spec
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1.7 mm ±0.1). Refdes text is 1.0 mm (JLC silk floor).
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- **LED series resistors R37/R41/R42: 49.9 Ω → 330 Ω** (reused existing part
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C25104; R38 already 330). ~3.9 mA vs the blinding ~26 mA — closes item 1's
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resistor half. Green PWM (`_GRN_DUTY`) in gateware still applies to D6/D12; the
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@@ -34,7 +34,7 @@ lands 2×N off instead of correct.
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## How to reapply — copy this exact dict, don't reconstruct it from memory
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This is the complete, current correction set (all 16 parts). **Copy-paste
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This is the complete, current correction set (all 20 parts). **Copy-paste
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this block, don't retype it from the table below or from memory** — the one
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time it was retyped from a section of prose instead of copied whole, U4 got
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silently dropped and shipped with a wrong rotation.
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@@ -49,12 +49,17 @@ corrections = {
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'D1': -90, 'D4': -90, 'D5': -90, 'U12': -90, # SOT-23-6, reconstructed hypothesis
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'U1': -180, # SOT-23-5, confirmed (two -90 corrections)
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'U4': -90, # SOT-23-5, confirmed ("U4 is good")
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'Q1': 180, 'Q2': 180, # SOT-23 bottom layer, confirmed "upside down"
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'Q1': 180, 'Q2': 180, # SOT-23; moved bottom->F.Cu in the 2026-08-28 rework, +180 re-confirmed on the top side (JLC preview)
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'D2': -90, # custom footprint, confirmed "90 CW"
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'D3': 180, # SMA diode, confirmed "180"
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'C65': 180, # electrolytic cap, confirmed "180"
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'U2': -90, # SOT-583-8, confirmed "90 CW"
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'U3': 180, # custom SOT95P280X110-6N footprint, confirmed "180"
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# LED rework 2026-08-28: 7 LEDs -> reverse-mount 1206 (hardware:LED_1206_ReverseMount_Everlight_24-21),
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# and the "Moved all components to F.Cu" commit put every part (incl. the former bottom-layer D8/D9/Q1/Q2)
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# on the top side. Only the GREEN 24-21 parts (C2980185) need a flip — their die polarity is opposite the
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# red (C2892757) / yellow (C424133) parts of the SAME footprint, so D7/D11/D13 take NO correction.
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'D6': 180, 'D8': 180, 'D9': 180, 'D12': 180, # GREEN 24-21 only — confirmed via JLC placement preview 2026-08-28
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} # positive = CCW, negative = CW
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with open('re-bba-rb-cpl.csv', newline='') as f:
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@@ -100,8 +105,11 @@ it."
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entirely on that same weakened report. Treat both as **unverified**, not
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settled — re-check them in the placement preview before assembly. Do not
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cite "all large chips are right" as evidence again.
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- **D8, D9 (LED_0603, bottom layer)** — verified 2026-07-31 by tracing the
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circuit rather than by eye, see "D8/D9 polarity" below. No correction.
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- ~~**D8, D9 (LED_0603, bottom layer)** — no correction.~~ **SUPERSEDED
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2026-08-28.** D8/D9 were swapped to the reverse-mount 1206 footprint and moved
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to F.Cu; they now take **+180°** and live in the corrections table (green
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24-21, C2980185). The old "D8/D9 polarity" tracing section below is retained
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for the schematic-net polarity logic but its *rotation* conclusion is stale.
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- **J2 (HR911105A magjack, rot=90° in the PCB file)** — not a CPL-rotation
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question (J2 doesn't need per-part correction below, it's not in the CPL
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correction set), but its physical orientation was independently verified:
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@@ -127,12 +135,18 @@ Each row: designator, package, raw→corrected, confidence.
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| U12 | SOT-23-6 | 180° | **90°** | Reconstructed hypothesis — not independently re-confirmed |
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| U1 | SOT-23-5 | 180° | **0°** (two corrections: -90° then another -90°, user-confirmed both times) | **Confirmed** by direct user feedback, twice |
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| U4 | SOT-23-5 | 0° | **270°** (-90°, the same family correction as D1/D4/D5/U12) | **Confirmed** — user checked and said "U4 is good" after this delta, no second correction needed (unlike U1) |
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| Q1 | SOT-23 (bottom layer) | -90° | **90°** | **Confirmed** ("upside down" = 180°, direction-agnostic) |
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| Q2 | SOT-23 (bottom layer) | -90° | **90°** | **Confirmed** (same as Q1) |
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| Q1 | SOT-23 (now F.Cu; was bottom) | -90° | **90°** | **Confirmed** ("upside down" = 180°, direction-agnostic; +180 re-confirmed on top after the 2026-08-28 F.Cu move, JLC preview) |
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| Q2 | SOT-23 (now F.Cu; was bottom) | -90° | **90°** | **Confirmed** (same as Q1; re-confirmed on top 2026-08-28) |
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| D2 | custom `SON50P110X213X50-7` | 0° | **270°** | **Confirmed** ("90° clockwise") |
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| D3 | `Diode_SMD:D_SMA` | 180° | **0°** | **Confirmed** ("180°", direction-agnostic) |
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| C65 | `Capacitor_SMD:CP_Elec_6.3x7.7` | 0° | **180°** | **Confirmed** ("180°", direction-agnostic) |
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| U2 | SOT-583-8 | 180° | **90°** | **Confirmed** ("90° clockwise") |
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| D6 | `hardware:LED_1206_ReverseMount_Everlight_24-21` (green C2980185) | -90° | **90°** (+180°) | **Confirmed** (JLC preview 2026-08-28) |
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| D8 | `…24-21` (green C2980185) | 0° | **180°** (+180°) | **Confirmed** (JLC preview 2026-08-28) |
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| D9 | `…24-21` (green C2980185) | 180° | **0°** (+180°) | **Confirmed** (JLC preview 2026-08-28) |
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| D12 | `…24-21` (green C2980185) | -90° | **90°** (+180°) | **Confirmed** (JLC preview 2026-08-28) |
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| D7, D11 | `…24-21` (red C2892757) | -90° | **-90°** (none) | **Confirmed no correction** — same footprint as the green parts but opposite die polarity (JLC preview 2026-08-28) |
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| D13 | `…24-21` (yellow C424133) | -90° | **-90°** (none) | **Confirmed no correction** (JLC preview 2026-08-28) |
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**"Reconstructed hypothesis" parts (U7, U10, D1, D4, D5, U12) explained:**
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the user reported "SOIC and SOT chips are rotated 90°, direction unsure."
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@@ -137,6 +137,31 @@ Major work this session:
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convenience one-command multi-seed workflow needs debugging if
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wanted again.
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## V2 rework — silkscreen & mechanical (added 2026-08-28)
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Cosmetic/mechanical items for the in-progress V2 rework (EEPROM→93LC56B,
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reverse-mount LEDs, J3 slot already done). These are PCB-layout tasks, not
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schematic changes.
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- [ ] **1. Add the project name in silkscreen.** Put a "re-bba-rb" (or chosen
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project name/version) label on the board silkscreen so the assembled board
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is identifiable. Pick a copper-free spot; watch the JLC 1.0 mm min text
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height / 0.15 mm min line-width floor (same rule that just caught the LED
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refdes). Consider adding a small rev tag (e.g. "v2") next to it.
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- [ ] **2. Extend the board out to the ethernet socket so it sits flush with the
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GC.** Lengthen the board outline (Edge.Cuts) toward the RJ45/magjack (J2)
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end so the finished board reaches flush with the GameCube's shell instead
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of stopping short. Mechanical-only (move the board edge + any ground pour
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to suit); keep the SP1/J3 edge geometry fixed. Verify the new outline
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against the GC slot depth before ordering.
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- [ ] **3. Add back-side silkscreen legends for the LEDs.** Label what each LED
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means on **B.SilkS** (the back is the viewing side — reverse-mount LEDs
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emit through the board, top faces into the GC slot). Map from the current
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build: LEDG/D6 = heartbeat, LEDR/D7 = EXI activity, RGB D11 = rx / D12 =
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tx / D13 = ready, D8/D9 = USB/GC power handover indicators. Confirm the
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final per-LED meaning against `synth.py` + BRINGUP.md before lettering, and
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mind the same silk text-height/width floor as item 1.
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## Critical — ALL RESOLVED (schematic + PCB, verified 2026-07-18)
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- [x] **EXI DO/DI swapped at J3 — FIXED 2026-07-17** (all copper unchanged).
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File diff suppressed because it is too large
Load Diff
@@ -1,6 +1,6 @@
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{
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"board": {
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"active_layer": 0,
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"active_layer": 5,
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"active_layer_preset": "",
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"auto_track_width": true,
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"hidden_netclasses": [],
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@@ -53,7 +53,7 @@
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"board_outline_area",
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"ly_points"
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],
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"visible_layers": "ffffffff_ffffffff_ffffd575_575555a1",
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"visible_layers": "ffffffff_ffffffff_ffffffff_ffffffff",
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"zone_display_mode": 0
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},
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"git": {
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