WIP rewrite: clock the EXI bit engine from the EXI clock pin
Replaces 54 MHz oversampling with a slave clocked by EXI CLK itself:
exiclk posedge sample MOSI (Mode 3 samples on edge 2)
exiclk_n negedge drive MISO (must settle between the master's samples)
CS_N async reset for both
EXI CLK (pin 44) is at die (6,0) = global buffer net 6 on the 5k-sg48, so it
can drive a real clock network with no board change.
This removes the capture domain entirely. Bit-level timing no longer
crosses a clock boundary -- MISO is clock-to-Q instead of 3 ticks of a foreign
clock -- and the only crossings left are the byte FIFOs, which have a whole
byte-time (~296 ns) of slack rather than a fraction of a bit.
AsyncFIFO needs a posedge clock for its internal reset CDC, so the FIFO sides
use reset-less POSEDGE domains on the same pin; the engine pops on the posedge
and hands the byte to the negedge output stage through a register. The FIFOs
must not see CS: resetting one side of an AsyncFIFO desynchronises its gray
pointers.
Two bugs found and fixed along the way:
* one pop per byte boundary is all that is needed -- pops during the header
drain whatever the previous transaction left (replacing the CS-fall flush)
and the turnaround-byte push lands in data slot 0. No slot-threshold or
header-length logic at all.
* rx_byte/rx_valid had to become COMBINATIONAL. Registered, they need one
more clock edge, and after a transaction's final bit the clock stops and
CS rises -- so the last byte of every transaction was lost (a 4-byte write
landed as DE AD BE 00, a 34-byte TX as 15 bytes).
At the HARDWARE rate (EXI_HALF=1, 27 MHz) the device ID, NWAYS, PAR
read/write and the W5100->SPRAM RX path now all pass -- none of which has ever
worked at 27 MHz before. Testbenches now drive the SPI clock with real
delays, since there is no capture domain to count ticks against.
STILL BROKEN: the SPRAM/DMA stream is offset by one byte (its round trip
exceeds the single turnaround byte), and TX lands 15 of 34 bytes. Do not
flash this yet.
Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
This commit is contained in:
+105
-257
@@ -1,292 +1,140 @@
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"""SPI Mode 3 byte-oriented slave for the EXI bus.
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"""SPI Mode 3 byte-oriented slave for the EXI bus — CLOCKED BY EXI CLK.
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CPOL=1, CPHA=1: CLK idles HIGH.
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Slave samples MOSI on the FALLING CLK edge.
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Slave drives MISO on the RISING CLK edge (master samples on next falling edge).
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All three raw inputs are run through a 2-stage FFSynchronizer before use.
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CPOL=1, CPHA=1 (real Mode 3): CLK idles HIGH, the master CHANGES MOSI on the
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falling edge and both ends SAMPLE on the rising edge.
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Architecture
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------------
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The engine is clocked by the EXI clock itself rather than oversampling it from
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a faster domain:
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exiclk posedge of EXI CLK — sample MOSI, assemble RX bytes
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exiclk_n negedge of EXI CLK — drive MISO (must change BETWEEN the
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master's sampling edges)
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CS_N asynchronous reset for both
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Why, and what it fixes (hardware 2026-10-03)
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--------------------------------------------
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The previous version oversampled EXI CLK from a 54 MHz `capture` domain, which
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put BIT-level timing across a clock-domain boundary: the engine's view of the
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clock lagged the pin by 2 stages of `FFSynchronizer` plus a register, ~3 ticks
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≈ 55 ns. One EXI bit at 27 MHz is 37 ns, so MISO came out ~2 bits late and the
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master read `0x17` as `05 C0` (= `0x17 >> 2`). Register reads were correct up
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to 4 MHz and failed from 8 MHz — the sweep read `ok=[1,1,1,0,0,0]`.
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No amount of oversampling fixes that: at 54 MHz there are only 2 ticks per bit,
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and the design cannot close the 81 MHz that 3x would need. Clocking the engine
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from the EXI pin makes MISO clock-to-Q instead, and moves the ONLY remaining
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crossing to the byte-level AsyncFIFOs, which have a whole byte-time (~296 ns at
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27 MHz) of slack instead of a fraction of a bit.
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EXI CLK (pin 44) sits at die (6,0) on the 5k-sg48, which is global buffer input
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net 6 — so it can drive a real clock network with no board change.
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The domains are created by the PARENT (`ExiCapture`) so the byte FIFOs can name
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them; this module just uses `m.d.exiclk` / `m.d.exiclk_n`.
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"""
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from amaranth import *
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from amaranth.lib.cdc import FFSynchronizer
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# ── public re-export for import convenience ─────────────────────────────────
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__all__ = ["SPIMode3Slave"]
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class SPIMode3Slave(Elaboratable):
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"""Byte-oriented SPI Mode 3 slave.
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"""Byte-oriented SPI Mode 3 slave, clocked by the EXI clock.
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Ports
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-----
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spi_clk / spi_mosi / spi_cs_n : raw async inputs from GC (synchronized internally)
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spi_miso : output to GC; idles HIGH when CS deasserted
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rx_byte : last complete received byte (valid when rx_valid pulses)
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rx_valid : 1-cycle pulse in exi domain when rx_byte contains a new byte
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tx_byte : upstream loads this before or within one exi clock of tx_load pulsing
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tx_load : 1-cycle pulse requesting the next TX byte from upstream
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spi_clk / spi_mosi / spi_cs_n : raw inputs from the GC. spi_clk drives the
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exiclk/exiclk_n domains and spi_cs_n their async reset (both wired by
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the parent); they are still listed here so the module is self-describing
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and so spi_cs_n can gate MISO combinationally.
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spi_miso : output to the GC; idles HIGH while CS is deasserted.
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rx_byte : last complete received byte (valid while rx_valid is high)
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rx_valid : 1-cycle pulse in `exiclk` when rx_byte holds a new byte
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tx_byte : byte to transmit; sampled at each byte boundary
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tx_load : 1-cycle pulse in `exiclk_n` asking upstream for the next byte
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hdr_bytes : how many leading bytes are header (MISO don't-care). Pops are
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suppressed until past them, so the first response byte the register
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file pushes lands in data slot 0 rather than being eaten by the header.
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"""
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def __init__(self, domain="capture", mode2=False):
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# Clock domain this byte engine runs in. Split-domain design puts the
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# bit engine in a fast `capture` domain (54 MHz) so it can oversample
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# a 27 MHz EXI clock ~3×; the register file lives in a slower domain.
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self._domain = domain
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# False = real Mode 3 (sample MOSI on RISING) -- what the GameCube
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# needs. True = the old Mode-2 behaviour the Pi probe was built on.
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self._mode2 = mode2
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def __init__(self):
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self.spi_clk = Signal(init=1) # idles HIGH
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self.spi_mosi = Signal()
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self.spi_cs_n = Signal(init=1) # active LOW
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self.spi_miso = Signal() # combinatorial output
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self.spi_miso = Signal(init=1)
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self.rx_byte = Signal(8)
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self.rx_valid = Signal()
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self.tx_byte = Signal(8)
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self.tx_load = Signal()
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# 1-cycle pulse on CS assertion (transaction start). The capture
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# wrapper uses it to reset its per-transaction TX byte counter.
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self.frame_start = Signal()
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# Header length for this transaction, in bytes. The real protocol has
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# two forms selected by bit 7 of byte 0 (see docs/exi_protocol_real.md):
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# register space = 4-byte header, command space = 2-byte.
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self.hdr_bytes = Signal(3, init=4)
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# Level: high while CS is asserted (a transaction is in progress).
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# Lets downstream logic detect variable-length (DMA) transaction ends.
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self.cs_active = Signal()
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# Transaction framing, generated in the slow domain by the parent.
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self.frame_start = Signal()
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self.cs_active = Signal()
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def elaborate(self, platform):
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m = Module()
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d = self._domain
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# ── Input synchronization (async → exi, 2 stages) ──────────────────
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clk_s = Signal(init=1)
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mosi_s = Signal()
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cs_s = Signal(init=1)
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m.submodules.sync_clk = FFSynchronizer(self.spi_clk, clk_s, o_domain=d, init=1)
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m.submodules.sync_mosi = FFSynchronizer(self.spi_mosi, mosi_s, o_domain=d)
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m.submodules.sync_cs = FFSynchronizer(self.spi_cs_n, cs_s, o_domain=d, init=1)
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# ── Edge detection ──────────────────────────────────────────────────
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clk_prev = Signal(init=1)
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cs_prev = Signal(init=1)
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m.d[d] += clk_prev.eq(clk_s)
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m.d[d] += cs_prev.eq(cs_s)
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falling_clk = Signal()
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rising_clk = Signal()
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cs_fall = Signal()
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cs_rise = Signal()
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# ⚠️ EDGE CONVENTION. The docs call this "Mode 3 (CPOL=1, CPHA=1)" but
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# then describe sampling MOSI on the FALLING edge -- that combination
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# is Mode 2. Real Mode 3 samples on the SECOND edge of each cycle,
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# which with an idle-high clock is the RISING one.
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#
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# Hardware 2026-10-03: the GameCube drives MOSI on the falling edge, so
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# sampling there latches the PREVIOUS bit -- every byte arrived one bit
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# late in both directions at every clock speed (header 0x80 was read as
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# 0x00, and the reply came back as 04 02 02 00 >> 1 = 02 01 01 00).
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# `mode2=True` restores the old behaviour, which is what the Pi probe
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# on J4 was written to match.
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if self._mode2:
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sample_edge, shift_edge = ~clk_s & clk_prev, clk_s & ~clk_prev
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else:
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sample_edge, shift_edge = clk_s & ~clk_prev, ~clk_s & clk_prev
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m.d.comb += falling_clk.eq(sample_edge) # "sample MOSI / advance bit"
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m.d.comb += rising_clk .eq(shift_edge) # "shift MISO / re-arm"
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m.d.comb += cs_fall .eq(~cs_s & cs_prev)
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m.d.comb += cs_rise .eq( cs_s & ~cs_prev)
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m.d.comb += self.frame_start.eq(cs_fall)
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m.d.comb += self.cs_active.eq(~cs_s)
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# ── Shift registers ─────────────────────────────────────────────────
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# ── RX: sample MOSI on the RISING edge (Mode 3 samples on edge 2) ──
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rx_shift = Signal(8)
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rx_bit = Signal(3)
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byte_idx = Signal(3, init=0) # bytes seen this transaction (saturating)
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nxt = Cat(self.spi_mosi, rx_shift[:-1]) # MSB-first: shift left, new bit at LSB
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m.d.exiclk += rx_shift.eq(nxt)
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m.d.exiclk += rx_bit.eq(rx_bit + 1)
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with m.If(rx_bit == 7):
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with m.If(byte_idx != 7):
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m.d.exiclk += byte_idx.eq(byte_idx + 1)
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# rx_byte/rx_valid are COMBINATIONAL, not registered. The clock stops
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# and CS rises immediately after a transaction's final bit, so a
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# registered pulse would need one more clock edge that never arrives
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# and the LAST byte of every transaction would be silently lost
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# (symptom: a 4-byte write landed as DE AD BE 00, and a 34-byte TX
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# stream as 15 bytes). Driving them combinationally makes the FIFO
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# capture the byte on the very edge that completes it.
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m.d.comb += self.rx_byte .eq(nxt)
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m.d.comb += self.rx_valid.eq(rx_bit == 7)
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# ── TX: pop on the POSEDGE, present on the NEGEDGE ────────────────
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# AsyncFIFO needs a posedge clock internally, so the FIFO is read in
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# `exiclk` and the byte is handed to the negedge side through a plain
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# register. posedge -> negedge of the SAME clock is a half-period
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# path (18.5 ns at 27 MHz), which is ample.
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#
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# One pop per byte boundary, unconditionally. The byte popped at the
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# end of byte N is presented during byte N+1, so:
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# - pops during the header drain whatever the previous transaction
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# left in the FIFO (this replaces the old CS-fall flush), and
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# - the response the register file pushes during the protocol's
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# turnaround byte is popped at that byte's end and lands in data
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# slot 0, exactly where it belongs.
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# No header-length or slot-threshold logic is needed at all.
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tx_hold = Signal(8)
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m.d.comb += self.tx_load.eq(rx_bit == 7)
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with m.If(rx_bit == 7):
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m.d.exiclk += tx_hold.eq(self.tx_byte)
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# MISO must settle on the falling edge, before the master samples it
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# on the rising one. Driving it on the rising edge is one bit late by
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# construction -- that was the 05 C0 bug.
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tx_shift = Signal(8)
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bit_ctr = Signal(4) # counts 0..7; 7 means "8th (last) bit"
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armed = Signal(init=1) # between bytes: drive the LIVE tx_byte MSB
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rearm = Signal() # arm for next byte on the next rising edge
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# MISO: idle HIGH when CS deasserted. While "armed" — i.e. at the start
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# of a byte, including the inter-byte / clock-idle gap before the first
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# falling edge — drive the LIVE tx_byte MSB. This is what lets a
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# response that upstream pushes DURING the EXI clock-idle gap reach MISO
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# in time: there is no clock edge during the gap to latch it, so MISO
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# must be combinational on tx_byte until the byte actually starts. Once
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# shifting (after the first falling edge) drive the latched shift reg.
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m.d.comb += self.spi_miso.eq(
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Mux(cs_s, 1, Mux(armed, self.tx_byte[7], tx_shift[7]))
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)
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# Default: deassert single-cycle pulses every cycle
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m.d[d] += self.rx_valid.eq(0)
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m.d[d] += self.tx_load.eq(0)
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with m.If(cs_fall):
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# Transaction start: first byte drives its MSB live (armed).
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m.d[d] += bit_ctr.eq(0)
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m.d[d] += armed.eq(1)
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with m.Elif(cs_rise | cs_s):
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# CS deasserted / idle: reset state
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m.d[d] += bit_ctr.eq(0)
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m.d[d] += armed.eq(1)
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tx_bit = Signal(3)
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m.d.exiclk_n += tx_bit.eq(tx_bit + 1)
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with m.If(tx_bit == 0):
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m.d.exiclk_n += tx_shift.eq(tx_hold) # first falling edge: MSB
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with m.Else():
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# CS asserted: run bit engine
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with m.If(falling_clk):
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# Sample MOSI (MSB first: left-shift, new bit enters at LSB)
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# Cat(a, b) → a at lower bits; so Cat(mosi, rx[6:0]) = {rx[6:0], mosi}
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m.d[d] += rx_shift.eq(Cat(mosi_s, rx_shift[:-1]))
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m.d.exiclk_n += tx_shift.eq(Cat(0, tx_shift[:-1]))
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with m.If(armed):
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# First falling edge of this byte: master has just sampled
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# the MSB (driven live above). Latch tx_byte so the
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# remaining 7 bits shift out of a stable register.
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m.d[d] += tx_shift.eq(self.tx_byte)
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m.d[d] += armed.eq(0)
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with m.If(bit_ctr == 7):
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# 8th falling edge: byte complete. The master samples the
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# LSB on THIS edge, so MISO must still hold tx_shift[7].
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# Defer arming to the next rising edge (rearm) so MISO is
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# not switched to the next byte's live MSB too early.
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m.d[d] += self.rx_byte.eq(Cat(mosi_s, rx_shift[:-1]))
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m.d[d] += self.rx_valid.eq(1)
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m.d[d] += bit_ctr.eq(0)
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m.d[d] += self.tx_load.eq(1) # advance source to next byte
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m.d[d] += rearm.eq(1) # arm on the next rising edge
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with m.Else():
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m.d[d] += bit_ctr.eq(bit_ctr + 1)
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with m.If(rising_clk):
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with m.If(rearm):
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# Byte boundary: arm for the next byte (live MSB drive).
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m.d[d] += armed.eq(1)
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m.d[d] += rearm.eq(0)
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with m.Elif(~armed):
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# Shift left: next bit into MSB position
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# Cat(0, tx[6:0]) = {tx[6:0], 0} — left shift
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m.d[d] += tx_shift.eq(Cat(0, tx_shift[:-1]))
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m.d.comb += self.spi_miso.eq(Mux(self.spi_cs_n, 1, tx_shift[7]))
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return m
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# ── Testbench ───────────────────────────────────────────────────────────────
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if __name__ == "__main__":
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from amaranth.sim import Simulator, Period
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dut = SPIMode3Slave()
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# 4 exi ticks per SPI half-period → well above the 3-cycle (2 sync + 1 edge) latency.
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HALF = 4
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async def spi_send_byte(ctx, mosi_val, next_tx_byte=None):
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"""Drive one SPI Mode 3 byte on MOSI; return the MISO byte assembled.
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next_tx_byte: if given, written to tx_byte after the LAST falling edge
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(before the last rising edge) so need_reload picks it up in time.
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"""
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miso_byte = 0
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for bit in range(7, -1, -1):
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ctx.set(dut.spi_mosi, (mosi_val >> bit) & 1)
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ctx.set(dut.spi_clk, 0) # falling edge
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await ctx.tick("capture").repeat(HALF)
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miso_byte = (miso_byte << 1) | ctx.get(dut.spi_miso)
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# Set next TX byte here — after last fall, before rising edge.
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# The rising edge is detected 3 cycles after we assert clk=1,
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# so we have HALF ticks of margin.
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if bit == 0 and next_tx_byte is not None:
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ctx.set(dut.tx_byte, next_tx_byte)
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ctx.set(dut.spi_clk, 1) # rising edge
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await ctx.tick("capture").repeat(HALF)
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return miso_byte
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errors = []
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async def testbench(ctx):
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# ── Test 1: Single byte TX/RX ──────────────────────────────────────
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ctx.set(dut.spi_cs_n, 0)
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ctx.set(dut.spi_clk, 1)
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ctx.set(dut.tx_byte, 0xA5) # pre-load before CS fall is detected
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await ctx.tick("capture").repeat(HALF)
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miso = await spi_send_byte(ctx, 0x37)
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await ctx.tick("capture").repeat(2)
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rx = ctx.get(dut.rx_byte)
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ctx.set(dut.spi_cs_n, 1)
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await ctx.tick("capture").repeat(HALF)
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if rx != 0x37:
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errors.append(f"Test1 rx_byte: expected 0x37, got 0x{rx:02X}")
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if miso != 0xA5:
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errors.append(f"Test1 miso: expected 0xA5, got 0x{miso:02X}")
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print(f"Test1 – MOSI→rx_byte: 0x{rx:02X} MISO←tx_byte: 0x{miso:02X}")
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await ctx.tick("capture").repeat(HALF)
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# ── Test 2: Two-byte transaction; second byte loaded via need_reload ─
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ctx.set(dut.spi_cs_n, 0)
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ctx.set(dut.tx_byte, 0xBE) # first response byte
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await ctx.tick("capture").repeat(HALF)
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# Pass next_tx_byte=0xEF so it's set after last falling edge of byte 0,
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# giving need_reload time to load it on the subsequent rising edge.
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miso0 = await spi_send_byte(ctx, 0x00, next_tx_byte=0xEF)
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miso1 = await spi_send_byte(ctx, 0xFF)
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await ctx.tick("capture").repeat(2)
|
||||
rx1 = ctx.get(dut.rx_byte)
|
||||
|
||||
ctx.set(dut.spi_cs_n, 1)
|
||||
await ctx.tick("capture").repeat(HALF)
|
||||
|
||||
if miso0 != 0xBE:
|
||||
errors.append(f"Test2 miso0: expected 0xBE, got 0x{miso0:02X}")
|
||||
if miso1 != 0xEF:
|
||||
errors.append(f"Test2 miso1: expected 0xEF, got 0x{miso1:02X}")
|
||||
if rx1 != 0xFF:
|
||||
errors.append(f"Test2 rx1: expected 0xFF, got 0x{rx1:02X}")
|
||||
print(f"Test2 – byte0 MISO: 0x{miso0:02X} byte1 MISO: 0x{miso1:02X} rx1: 0x{rx1:02X}")
|
||||
|
||||
await ctx.tick("capture").repeat(HALF)
|
||||
|
||||
# ── Test 3: MISO idles HIGH when CS deasserted ─────────────────────
|
||||
miso_idle = ctx.get(dut.spi_miso)
|
||||
if miso_idle != 1:
|
||||
errors.append(f"Test3 MISO idle: expected 1, got {miso_idle}")
|
||||
print(f"Test3 – MISO idle (CS=1): {miso_idle}")
|
||||
|
||||
# ── Test 4: All-zeros byte (0x00) TX and RX ────────────────────────
|
||||
ctx.set(dut.spi_cs_n, 0)
|
||||
ctx.set(dut.tx_byte, 0x00)
|
||||
await ctx.tick("capture").repeat(HALF)
|
||||
|
||||
miso = await spi_send_byte(ctx, 0xFF)
|
||||
await ctx.tick("capture").repeat(2)
|
||||
rx = ctx.get(dut.rx_byte)
|
||||
ctx.set(dut.spi_cs_n, 1)
|
||||
await ctx.tick("capture").repeat(HALF)
|
||||
|
||||
if miso != 0x00:
|
||||
errors.append(f"Test4 miso: expected 0x00, got 0x{miso:02X}")
|
||||
if rx != 0xFF:
|
||||
errors.append(f"Test4 rx: expected 0xFF, got 0x{rx:02X}")
|
||||
print(f"Test4 – 0x00 TX / 0xFF RX: MISO=0x{miso:02X} rx=0x{rx:02X}")
|
||||
|
||||
sim = Simulator(dut)
|
||||
sim.add_clock(Period(MHz=54), domain="capture")
|
||||
sim.add_testbench(testbench)
|
||||
|
||||
with sim.write_vcd("SPIMode3Slave.vcd"):
|
||||
sim.run()
|
||||
|
||||
if errors:
|
||||
print("\nFAILURES:")
|
||||
for e in errors:
|
||||
print(" ", e)
|
||||
raise SystemExit(1)
|
||||
else:
|
||||
print("\nAll tests passed.")
|
||||
|
||||
Reference in New Issue
Block a user