From a5e1adbff3f30ac2c51b43c79445324f438cc203 Mon Sep 17 00:00:00 2001 From: Dennis Brentjes Date: Sat, 18 Jul 2026 13:07:01 +0000 Subject: [PATCH] TODO: resolve D4/D5 question - keep USBLC6 flow-through as designed Record the verdict so it isn't relitigated: USBLC6 is ST-rated for Ethernet, PHY-side placement is standard practice, floating VBUS is deliberate (3.3V-biased lines would clip against a tied rail), and the split PHY_*/ETH_* nets force zero-stub flow-through routing - the better ESD topology. Earlier stub/DNP suggestion withdrawn. Co-Authored-By: Claude Fable 5 --- hardware/re-bba-rb/TODO.md | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/hardware/re-bba-rb/TODO.md b/hardware/re-bba-rb/TODO.md index 148d53e..aa3975d 100644 --- a/hardware/re-bba-rb/TODO.md +++ b/hardware/re-bba-rb/TODO.md @@ -39,9 +39,20 @@ W5100S reference schematic, and JLCPCB manufacturing limits. ERC/DRC: clean. in each line (WIZnet note 6, EMI reduction) — would require breaking the pairs; add only if EMI testing demands. - [ ] Place C51/C52 physically at J2 pins 4/5 (center taps). - - [ ] Reconsider D4/D5 (USBLC6 on the line side of the magnetics): - unusual — transformer already isolates; their VBUS pins float so - they only clamp to GND. Remove or justify. + - [x] D4/D5 (USBLC6 on the PHY pairs) — RESOLVED 2026-07-17: **keep, + exactly as drawn.** ST explicitly rates USBLC6 for Ethernet; + PHY-side placement guards residual coupling through the + transformer; 2.5–3.5 pF/line is fine at 100BASE-TX. Two + deliberate details, do not "fix": (1) pin 5 (VBUS) floats ON + PURPOSE — the lines carry ~3.3 V DC bias (center taps) and swing + above it; a 3.3 V-tied rail would clip signal peaks. Floating, + the rail self-biases to the line peak and the internal 6 V zener + still clamps strikes. (2) The split nets (PHY_* vs ETH_*) force + FLOW-THROUGH routing (pins 1→6, 3→4 are one internal node) — + zero-stub clamping; do NOT merge the nets or tap the diode as a + stub (stub inductance adds L·di/dt let-through). Layout: route + the pair in-line through the package, near J2, short GND via on + pin 2. If ever bypassing at bring-up: desolder + jumper 1–6/3–4. - [ ] **FT2232H EEPROM interface** (`Usb Connector.kicad_sch`) — schematic part DONE 2026-07-17 per datasheet Table 3.4: U7.4 (DO) moved to new net EE_DO; R30 (2.2 kΩ, C25879) inserted EE_DO→EE_DATA; R31 (10 kΩ,