Started on component selection of the final PCB.

2026-06-13 21:58:06 +02:00
parent 5b732a0b34
commit a7c88109a9
22 changed files with 11239 additions and 578 deletions
@@ -98,11 +98,10 @@ All modules elaborate without errors and pass their unit tests. The full design
 **Bring-up status panel (optional):** `BBATop(status_panel=True)` adds a
 `StatusPanel` driving onboard iCEbreaker LEDs + button (dedicated pins, so it
 coexists with EXI + W5100). `synth.py` enables it: **LEDG=heartbeat**,
-**LEDR=EXI activity** (the GC is talking), **BTN_N=manual re-init**. The full
-EXI + W5100 + panel build synthesizes and meets timing (slow ~35≥24, capture
-~64≥54, 44% LC). Panel LEDs 3–5 (rx/tx/ready) exist in the module but aren't
-mapped on the iCEbreaker (only 2 discrete LEDs); the onboard RGB or a custom
-PCB can expose them.
+**LEDR=EXI activity** (the GC is talking), **RGB red=rx / green=tx / blue=ready**
+(via `SB_RGBA_DRV` on pins 39/40/41), **BTN_N=manual re-init**. All 5 panel
+LEDs are now mapped on the iCEbreaker. The full EXI + W5100 + panel build
+synthesizes and meets timing (slow ~35≥24, capture ~64≥54, 44% LC).

 **Ethernet back-end is selectable:** `BBATop(eth="w5100")` (default — indirect
 parallel bus, reaches the ~27 Mbit/s EXI ceiling) or `BBATop(eth="w5500")` (SPI,