Rework the eFuse schematic for readability; 3-resistor OVLO divider

Redraws the eFuse area with proper wires instead of labels-on-pins, and
simplifies the divider that 228ff03 added.

The first draft split R3 into 12 k + 2.2 k to hit 14.2 k, purely to preserve
the original ~8.9 V UVLO.  That bought a fourth resistor and a named junction
net (EFUSE_R3MID) that nothing else touched.  The ~9 V UVLO turned out to be
an assumption carried over from the original design rather than a requirement:
U3's minimum input is 4.5 V, so relaxing it to 6.78 V costs nothing and is in
fact less likely to chatter if the GC rail sags.

  R46  620 k -> 100 k   (C25741)   R1: 12V_RAW -> EN/UVLO
  R47  100 k -> 12.4 k  (C11692)   R2: EN/UVLO -> OVLO
  R48  NEW      10 k    (C25744)   R3: OVLO -> GND
  R49  removed
  R45  100 k -> 33 k    (C25779)   ILIM 0.52 A -> 1.52 A

OVLO is unchanged at 15.18 V typ (14.47-15.78 worst case) against U3's 17 V
limit, so the simplification costs nothing on the parameter that matters.

Verified: 12V_RAW(R46.2) / EFUSE_EN(R46.1,R47.1,U13.5) / EFUSE_OVLO(R47.2,
R48.1,U13.2) / GND(R48.2,R45.2,U13.4); 152 -> 151 components with only R49
removed; ERC 0 violations.

Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>

hardware/re-bba-rb/REVIEW.md

@@ -323,16 +323,25 @@ datasheet extraction, WebSearch/WebFetch for parts and reference designs.
       VIN(OV) = VOVLO(R) × (R1+R2+R3)/R3           (eq 8),  both thresholds 1.24 V
   | ref | was | becomes | LCSC | already on board as |
   |---|---|---|---|---|
-  | R46 (R1, 12V_RAW→EN/UVLO) | 620 k | **150 k** | C93947 | R3 |
+  | R46 (R1, 12V_RAW→EN/UVLO) | 620 k | **100 k**  | C25741 | R4 |
-  | R47 (R2, EN/UVLO→OVLO)    | 100 k | **10 k**  | C25744 | R2, R9, R11, … |
+  | R47 (R2, EN/UVLO→OVLO)    | 100 k | **12.4 k** | C11692 | R16 |
-  | R48 (R3a, OVLO→GND) NEW   | —     | **12 k**  | C25752 | R10 |
+  | R48 (R3, OVLO→GND) NEW    | —     | **10 k**   | C25744 | R2, R9, R11, … |
-  | R49 (R3b, series w/ R48) NEW | —  | **2.2 k** | C25879 | R30 |
+
-  R3 = 12 k + 2.2 k = 14.2 kΩ. Results across tolerance (VOVLO 1.20/1.24/1.27):
+  Results across tolerance (VOVLO 1.20/1.24/1.27): **UVLO 6.78 V (6.56–6.94)**
-  **UVLO 8.93 V typ (8.64–9.14)** — identical to the current board, so turn-on
+  and **OVLO 15.18 V typ (14.47–15.78 including 1% resistors)**.  String current
-  behaviour is unchanged — and **OVLO 15.21 V typ (14.72–15.58)**, worst case
+  98 µA at 12 V (TI requires ≥20× the 0.1 µA pin leakage, i.e. ≥2 µA).  OVLO pin
-  with 1% resistors **15.81 V**.  String current 68.9 µA at 12 V (TI requires
+  sits at 0.98 V at 12 V and 1.55 V at 19 V — far under its 6.5 V abs max, the
-  ≥20× the 0.1 µA pin leakage, i.e. ≥2 µA).  OVLO pin sits at 0.98 V at 12 V and
+  lowest-rated pin on the part; EN/UVLO reaches 3.48 V at 19 V against its 20 V
-  1.55 V at 19 V — far under its 6.5 V abs max, the lowest-rated pin on the part.
+  max.
+
+  **UVLO drops from today's 8.93 V to 6.78 V, and that is fine.** U3's minimum
+  input is 4.5 V, so the buck is well inside its range at 6.78 V; UVLO is not
+  load-bearing here, and a lower threshold is *less* likely to chatter if the GC
+  rail sags under disc-motor load.  An earlier draft held UVLO at ~8.9 V and paid
+  for it with a FOURTH resistor (R3 split into 12 k + 2.2 k = 14.2 k), which also
+  created a pointless named junction net.  The ~9 V figure was an assumption
+  carried over from the original design, not a requirement — **do not re-split
+  R3 to chase it**.
 
   **The OVLO ceiling is set by U3, not by the eFuse.** The TPS562201 buck is
   rated **4.5–17 V** input (19 V abs max), so OVLO must disconnect before the

hardware/re-bba-rb/TODO.md

@@ -249,21 +249,24 @@ schematic changes.
       **SCHEMATIC DONE 2026-10-02 (netlist + ERC verified) — PCB PLACEMENT
       AND ROUTING STILL TO DO.** TI 3-resistor ladder (§8.2.3.2), EN/UVLO tapped at
       R1–R2 and OVLO at R2–R3, plus an ILIM correction:
-        R46  620 k -> **150 k**  (C93947)    R1, top: 12V_RAW -> EN/UVLO
+        R46  620 k -> **100 k**  (C25741)    R1, top: 12V_RAW -> EN/UVLO
-        R47  100 k -> **10 k**   (C25744)    R2: EN/UVLO -> OVLO
+        R47  100 k -> **12.4 k** (C11692)    R2: EN/UVLO -> OVLO
-        R48  NEW   -> **12 k**   (C25752)  \ R3 = 14.2 k in series,
+        R48  NEW   -> **10 k**   (C25744)    R3: OVLO -> GND
-        R49  NEW   -> **2.2 k**  (C25879)  /      OVLO -> GND
         R45  100 k -> **33 k**   (C25779)    ILIM 0.52 A -> 1.52 A
         U13 pin 2 (OVLO): disconnected from GND, now on net EFUSE_OVLO.
-      Verified after the edit: nets are 12V_RAW(R46.1) / EFUSE_EN(R46.2, R47.1,
+      **Three resistors, not four** - an earlier draft split R3 into 12 k + 2.2 k
-      U13.5) / EFUSE_OVLO(R47.2, R48.1, U13.2) / EFUSE_R3MID(R48.2, R49.1) /
+      to hit 14.2 k, which created a pointless named junction net. Relaxing the
-      GND(R49.2, R45.2, U13.4); component count 150 -> 152 with nothing
+      UVLO target (it was an assumption, not a requirement) allows a single
-      dropped; ERC 0 violations.  **PCB TODO:** place R48/R49 near U13, route
+      stocked 10 k for R3 at essentially the same OVLO. Do not re-split it.
-      the new EFUSE_OVLO and EFUSE_R3MID nets, and re-export BOM + CPL
+      Verified after the edit: nets are 12V_RAW(R46.2) / EFUSE_EN(R46.1, R47.1,
-      (reapplying CPL_ROTATIONS.md afterwards).
+      U13.5) / EFUSE_OVLO(R47.2, R48.1, U13.2) / GND(R48.2, R45.2, U13.4);
-      Gives UVLO 8.93 V typ (unchanged from today) and OVLO 15.21 V typ,
+      component count 150 -> 151 with nothing dropped; ERC 0 violations.
-      15.81 V worst case — under U3's 17 V input rating, which is what actually
+      **PCB TODO:** place R48 near U13, route the new EFUSE_OVLO net, and
-      caps the OVLO target. ILIM must exceed the board's own 621 mA inrush;
+      re-export BOM + CPL (reapplying CPL_ROTATIONS.md afterwards).
+      Gives **UVLO 6.78 V** and **OVLO 15.18 V typ (14.47–15.78 worst case)**
+      — under U3's 17 V input rating, which is what actually caps the OVLO
+      target. UVLO sits well above U3's 4.5 V minimum, so the lower value is
+      harmless and is in fact less prone to chattering if the GC rail sags. ILIM must exceed the board's own 621 mA inrush;
       0.52 A did not, so the part current-limited on every power-on.
       **Every value is already on the BOM and 620 k loses its only user, so this
       is one FEWER unique part, +2 placements.** Full derivation, tolerance

hardware/re-bba-rb/re-bba-rb.kicad_pro

@@ -957,7 +957,7 @@
         "uuid": "dbb182a6-d579-468e-b98b-6f0950da9e3a"
       }
     ],
-    "used_designators": "C17,#PWR090e1-3,#PWR44-50,R20-21",
+    "used_designators": "C17,#PWR090e1-3,#PWR44-50,#PWR54,R20-21",
     "variants": []
   },
   "sheets": [