Rework the eFuse schematic for readability; 3-resistor OVLO divider

Redraws the eFuse area with proper wires instead of labels-on-pins, and
simplifies the divider that 228ff03 added.

The first draft split R3 into 12 k + 2.2 k to hit 14.2 k, purely to preserve
the original ~8.9 V UVLO.  That bought a fourth resistor and a named junction
net (EFUSE_R3MID) that nothing else touched.  The ~9 V UVLO turned out to be
an assumption carried over from the original design rather than a requirement:
U3's minimum input is 4.5 V, so relaxing it to 6.78 V costs nothing and is in
fact less likely to chatter if the GC rail sags.

  R46  620 k -> 100 k   (C25741)   R1: 12V_RAW -> EN/UVLO
  R47  100 k -> 12.4 k  (C11692)   R2: EN/UVLO -> OVLO
  R48  NEW      10 k    (C25744)   R3: OVLO -> GND
  R49  removed
  R45  100 k -> 33 k    (C25779)   ILIM 0.52 A -> 1.52 A

OVLO is unchanged at 15.18 V typ (14.47-15.78 worst case) against U3's 17 V
limit, so the simplification costs nothing on the parameter that matters.

Verified: 12V_RAW(R46.2) / EFUSE_EN(R46.1,R47.1,U13.5) / EFUSE_OVLO(R47.2,
R48.1,U13.2) / GND(R48.2,R45.2,U13.4); 152 -> 151 components with only R49
removed; ERC 0 violations.

Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>

hardware/re-bba-rb/REVIEW.md

@@ -323,16 +323,25 @@ datasheet extraction, WebSearch/WebFetch for parts and reference designs.
       VIN(OV) = VOVLO(R) × (R1+R2+R3)/R3           (eq 8),  both thresholds 1.24 V
   | ref | was | becomes | LCSC | already on board as |
   |---|---|---|---|---|
-  | R46 (R1, 12V_RAW→EN/UVLO) | 620 k | **150 k** | C93947 | R3 |
-  | R47 (R2, EN/UVLO→OVLO)    | 100 k | **10 k**  | C25744 | R2, R9, R11, … |
-  | R48 (R3a, OVLO→GND) NEW   | —     | **12 k**  | C25752 | R10 |
-  | R49 (R3b, series w/ R48) NEW | —  | **2.2 k** | C25879 | R30 |
-  R3 = 12 k + 2.2 k = 14.2 kΩ. Results across tolerance (VOVLO 1.20/1.24/1.27):
-  **UVLO 8.93 V typ (8.64–9.14)** — identical to the current board, so turn-on
-  behaviour is unchanged — and **OVLO 15.21 V typ (14.72–15.58)**, worst case
-  with 1% resistors **15.81 V**.  String current 68.9 µA at 12 V (TI requires
-  ≥20× the 0.1 µA pin leakage, i.e. ≥2 µA).  OVLO pin sits at 0.98 V at 12 V and
-  1.55 V at 19 V — far under its 6.5 V abs max, the lowest-rated pin on the part.
+  | R46 (R1, 12V_RAW→EN/UVLO) | 620 k | **100 k**  | C25741 | R4 |
+  | R47 (R2, EN/UVLO→OVLO)    | 100 k | **12.4 k** | C11692 | R16 |
+  | R48 (R3, OVLO→GND) NEW    | —     | **10 k**   | C25744 | R2, R9, R11, … |
+
+  Results across tolerance (VOVLO 1.20/1.24/1.27): **UVLO 6.78 V (6.56–6.94)**
+  and **OVLO 15.18 V typ (14.47–15.78 including 1% resistors)**.  String current
+  98 µA at 12 V (TI requires ≥20× the 0.1 µA pin leakage, i.e. ≥2 µA).  OVLO pin
+  sits at 0.98 V at 12 V and 1.55 V at 19 V — far under its 6.5 V abs max, the
+  lowest-rated pin on the part; EN/UVLO reaches 3.48 V at 19 V against its 20 V
+  max.
+
+  **UVLO drops from today's 8.93 V to 6.78 V, and that is fine.** U3's minimum
+  input is 4.5 V, so the buck is well inside its range at 6.78 V; UVLO is not
+  load-bearing here, and a lower threshold is *less* likely to chatter if the GC
+  rail sags under disc-motor load.  An earlier draft held UVLO at ~8.9 V and paid
+  for it with a FOURTH resistor (R3 split into 12 k + 2.2 k = 14.2 k), which also
+  created a pointless named junction net.  The ~9 V figure was an assumption
+  carried over from the original design, not a requirement — **do not re-split
+  R3 to chase it**.
 
   **The OVLO ceiling is set by U3, not by the eFuse.** The TPS562201 buck is
   rated **4.5–17 V** input (19 V abs max), so OVLO must disconnect before the