Rework the eFuse schematic for readability; 3-resistor OVLO divider

Redraws the eFuse area with proper wires instead of labels-on-pins, and
simplifies the divider that 228ff03 added.

The first draft split R3 into 12 k + 2.2 k to hit 14.2 k, purely to preserve
the original ~8.9 V UVLO.  That bought a fourth resistor and a named junction
net (EFUSE_R3MID) that nothing else touched.  The ~9 V UVLO turned out to be
an assumption carried over from the original design rather than a requirement:
U3's minimum input is 4.5 V, so relaxing it to 6.78 V costs nothing and is in
fact less likely to chatter if the GC rail sags.

  R46  620 k -> 100 k   (C25741)   R1: 12V_RAW -> EN/UVLO
  R47  100 k -> 12.4 k  (C11692)   R2: EN/UVLO -> OVLO
  R48  NEW      10 k    (C25744)   R3: OVLO -> GND
  R49  removed
  R45  100 k -> 33 k    (C25779)   ILIM 0.52 A -> 1.52 A

OVLO is unchanged at 15.18 V typ (14.47-15.78 worst case) against U3's 17 V
limit, so the simplification costs nothing on the parameter that matters.

Verified: 12V_RAW(R46.2) / EFUSE_EN(R46.1,R47.1,U13.5) / EFUSE_OVLO(R47.2,
R48.1,U13.2) / GND(R48.2,R45.2,U13.4); 152 -> 151 components with only R49
removed; ERC 0 violations.

Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>

hardware/re-bba-rb/TODO.md

@@ -249,21 +249,24 @@ schematic changes.
       **SCHEMATIC DONE 2026-10-02 (netlist + ERC verified) — PCB PLACEMENT
       AND ROUTING STILL TO DO.** TI 3-resistor ladder (§8.2.3.2), EN/UVLO tapped at
       R1–R2 and OVLO at R2–R3, plus an ILIM correction:
-        R46  620 k -> **150 k**  (C93947)    R1, top: 12V_RAW -> EN/UVLO
-        R47  100 k -> **10 k**   (C25744)    R2: EN/UVLO -> OVLO
-        R48  NEW   -> **12 k**   (C25752)  \ R3 = 14.2 k in series,
-        R49  NEW   -> **2.2 k**  (C25879)  /      OVLO -> GND
+        R46  620 k -> **100 k**  (C25741)    R1, top: 12V_RAW -> EN/UVLO
+        R47  100 k -> **12.4 k** (C11692)    R2: EN/UVLO -> OVLO
+        R48  NEW   -> **10 k**   (C25744)    R3: OVLO -> GND
         R45  100 k -> **33 k**   (C25779)    ILIM 0.52 A -> 1.52 A
         U13 pin 2 (OVLO): disconnected from GND, now on net EFUSE_OVLO.
-      Verified after the edit: nets are 12V_RAW(R46.1) / EFUSE_EN(R46.2, R47.1,
-      U13.5) / EFUSE_OVLO(R47.2, R48.1, U13.2) / EFUSE_R3MID(R48.2, R49.1) /
-      GND(R49.2, R45.2, U13.4); component count 150 -> 152 with nothing
-      dropped; ERC 0 violations.  **PCB TODO:** place R48/R49 near U13, route
-      the new EFUSE_OVLO and EFUSE_R3MID nets, and re-export BOM + CPL
-      (reapplying CPL_ROTATIONS.md afterwards).
-      Gives UVLO 8.93 V typ (unchanged from today) and OVLO 15.21 V typ,
-      15.81 V worst case — under U3's 17 V input rating, which is what actually
-      caps the OVLO target. ILIM must exceed the board's own 621 mA inrush;
+      **Three resistors, not four** - an earlier draft split R3 into 12 k + 2.2 k
+      to hit 14.2 k, which created a pointless named junction net. Relaxing the
+      UVLO target (it was an assumption, not a requirement) allows a single
+      stocked 10 k for R3 at essentially the same OVLO. Do not re-split it.
+      Verified after the edit: nets are 12V_RAW(R46.2) / EFUSE_EN(R46.1, R47.1,
+      U13.5) / EFUSE_OVLO(R47.2, R48.1, U13.2) / GND(R48.2, R45.2, U13.4);
+      component count 150 -> 151 with nothing dropped; ERC 0 violations.
+      **PCB TODO:** place R48 near U13, route the new EFUSE_OVLO net, and
+      re-export BOM + CPL (reapplying CPL_ROTATIONS.md afterwards).
+      Gives **UVLO 6.78 V** and **OVLO 15.18 V typ (14.47–15.78 worst case)**
+      — under U3's 17 V input rating, which is what actually caps the OVLO
+      target. UVLO sits well above U3's 4.5 V minimum, so the lower value is
+      harmless and is in fact less prone to chattering if the GC rail sags. ILIM must exceed the board's own 621 mA inrush;
       0.52 A did not, so the part current-limited on every power-on.
       **Every value is already on the BOM and 620 k loses its only user, so this
       is one FEWER unique part, +2 placements.** Full derivation, tolerance