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Fix the +1 descriptor offset: drop the arbiter's response register

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SPRAMArbiter latched the SPRAM word into rsp_buf and raised exi_rsp_valid a
cycle later.  BBARegisterFile already took the response the cycle it arrived,
so the buffer bought nothing and cost a 24 MHz cycle (~42 ns) inside a deadline
that was short by about that much.  Both are now combinational in the cycle
SPRAM's output is valid.  The data sampling is unchanged -- the old code read
spram_dout in that same cycle, it just registered it before handing it over --
so only the handoff moved.

bba_top T9 goes from 1/6 to 6/6 byte-exact at EXI_HALF=1, and stays 6/6 at 2
and 8.  The whole suite passes at the hardware rate.  Nothing else changed:
BBARegisterFile is untouched.

Found by measuring instead of guessing, after four falsified attempts.  A
counter in ExiCapture recording tx_load & ~tx_fifo.r_rdy, with a shift-register
history of which byte boundary underran, showed good and bad reads BOTH
underrun at pop 3 (harmless, mid-header) while a bad read adds pop 4 -- the pop
that loads data slot 0.  So the late byte is the FIRST data byte, which rules
out every "prefetch further ahead" idea, because byte 0's request cannot be
issued before RHDR_LO where the low address byte arrives.  That makes the
deadline arithmetic with no contention in it: rx CDC ~125ns + arbiter 42 + SPRAM
42 + rsp_buf 42 + tx CDC ~110 = ~361ns against a 296ns byte time.  Over budget
idle, which is why fair arbitration changed nothing -- ETH contention was only
what pushed a marginal path over on some frames.

Two further changes were implemented, measured and then removed as unnecessary:
issuing byte 1's request during the pad byte, and two requests in flight with a
3-deep response hold.  With rsp_buf gone, T9 is 6/6 with both removed, with
either alone, and with the register file reverted completely.  They were real
pipelining but not the constraint, and they cost logic on sync, the binding
timing domain.  CLAUDE.md records them as do-not-re-add, along with the trap
that sank the earlier 2-outstanding attempt: incrementing `outstanding` in the
FSM and decrementing it in the response handler are two m.d.sync assignments
that Amaranth resolves by PRIORITY, not arithmetic, so the increment is
silently discarded when both fire in one cycle.

Arbiter TB updated (the response is a cycle earlier) and mutation-tested:
re-registering the response fails T1/T2/T4, swapping the byte lanes fails
T1/T2.  New T4 pins exi_rsp_valid to exactly one cycle.

Not yet confirmed on hardware; netboot's reader still probes both offsets.

Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
This commit is contained in:
Dennis Brentjes
2026-10-10 09:43:25 +02:00
parent 007c4d40f9
commit abab26232b
2 changed files with 126 additions and 45 deletions
Download Patch File Download Diff File Expand all files Collapse all files
exi_bba/spram_arbiter.py
+44 -19
View File
@@ -41,8 +41,9 @@ class SPRAMArbiter(Elaboratable):
exi_req_addr : 16-bit byte address to read
exi_req_valid : FIFO r_rdy — a request is waiting
exi_req_ready : FIFO r_en — pop the request (asserted when serviced)
exi_rsp_data : 8-bit result byte
exi_rsp_valid : FIFO w_en — push result when valid
exi_rsp_data : 8-bit result byte — COMBINATIONAL, valid only while
exi_rsp_valid is high; the consumer must take it that cycle
exi_rsp_valid : result is valid this cycle
ETH write interface (from RXFrameAssembler)
-------------------------------------------
@@ -120,7 +121,17 @@ class SPRAMArbiter(Elaboratable):
read_pending = Signal() # a read address was issued last cycle
read_was_odd = Signal() # byte address bit 0 of the pending read
rsp_buf = Signal(8) # registered response byte; valid when exi_rsp_valid
# The response is COMBINATIONAL in the cycle SPRAM's output is valid,
# not registered for one more. That register cost a 24 MHz cycle
# (~42 ns) inside the EXI read's deadline: the request for data byte 0
# cannot be issued before the header's low address byte has crossed
# the rx CDC, leaving ~296 ns for rx CDC (~125 ns) + this round trip +
# the tx CDC (~110 ns). With the extra register that totals ~361 ns
# and the engine's pop for data slot 0 found tx_fifo empty, resending
# the stale head (the duplicated-first-byte underrun). The consumer
# takes the response the cycle it is valid, so the buffer bought
# nothing.
# Combinatorial defaults
m.d.comb += [
@@ -130,13 +141,12 @@ class SPRAMArbiter(Elaboratable):
spram_addr .eq(0),
self.exi_req_ready.eq(0),
self.eth_wr_ready .eq(0),
self.exi_rsp_data .eq(rsp_buf), # always sourced from registered buffer
self.exi_rsp_valid.eq(read_pending),
self.exi_rsp_data .eq(Mux(read_was_odd,
spram_dout[8:16], spram_dout[0:8])),
]
# Registered defaults
m.d.sync += [
self.exi_rsp_valid.eq(0),
read_pending .eq(0),
]
m.d.sync += read_pending.eq(0)
# ETH write has priority
with m.If(self.eth_wr_valid):
@@ -167,14 +177,6 @@ class SPRAMArbiter(Elaboratable):
read_was_odd.eq(self.exi_req_addr[0]),
]
# Capture SPRAM output into registered buffer after 1-cycle latency
with m.If(read_pending):
with m.If(read_was_odd):
m.d.sync += rsp_buf.eq(spram_dout[8:16])
with m.Else():
m.d.sync += rsp_buf.eq(spram_dout[0:8])
m.d.sync += self.exi_rsp_valid.eq(1)
return m
@@ -206,8 +208,12 @@ if __name__ == "__main__":
ctx.set(dut.exi_req_valid, 1)
await ctx.tick("sync").repeat(1) # clock A: read issued, read_pending=1
ctx.set(dut.exi_req_valid, 0)
await ctx.tick("sync").repeat(1) # clock B: SPRAM output captured, valid=1
# Check HERE — exi_rsp_valid is 1 for exactly this one cycle
# Check HERE. The response is COMBINATIONAL: during the cycle after
# the issue, read_pending is high and SPRAM's output is valid, so
# exi_rsp_valid and exi_rsp_data are live RIGHT NOW. Waiting another
# tick reads zeros -- which is the regression this asserts against,
# since a registered response would need that extra tick and would
# cost the EXI read 42 ns it does not have.
rdata = ctx.get(dut.exi_rsp_data)
rvalid = ctx.get(dut.exi_rsp_valid)
@@ -231,9 +237,10 @@ if __name__ == "__main__":
ctx.set(dut.exi_req_valid, 1)
await ctx.tick("sync").repeat(1)
ctx.set(dut.exi_req_valid, 0)
await ctx.tick("sync").repeat(1)
rdata = ctx.get(dut.exi_rsp_data)
if not ctx.get(dut.exi_rsp_valid):
errors.append("T2 exi_rsp_valid not set")
if rdata != 0xCD:
errors.append(f"T2 odd addr read-back: expected 0xCD, got 0x{rdata:02X}")
print(f"T2 odd addr read-back: data=0x{rdata:02X}")
@@ -260,6 +267,24 @@ if __name__ == "__main__":
errors.append("T3 ETH priority: EXI read was not blocked")
print(f"T3 ETH priority: eth_won={eth_won} exi_blocked={exi_blocked}")
await ctx.tick("sync").repeat(2)
# T4: exi_rsp_valid is high for EXACTLY the one cycle after the issue.
# The consumer (BBARegisterFile) relies on that to count responses
# against requests in flight; a valid that lingered would be counted
# twice and insert a byte into the GC's read.
ctx.set(dut.exi_req_addr, 0x0100)
ctx.set(dut.exi_req_valid, 1)
await ctx.tick("sync").repeat(1)
ctx.set(dut.exi_req_valid, 0)
v_now = ctx.get(dut.exi_rsp_valid)
await ctx.tick("sync").repeat(1)
v_after = ctx.get(dut.exi_rsp_valid)
if not v_now or v_after:
errors.append(f"T4 rsp_valid window: now={v_now} after={v_after} "
f"(want 1 then 0)")
print(f"T4 rsp_valid one cycle only: now={v_now} after={v_after}")
sim = Simulator(dut)
sim.add_clock(Period(MHz=24), domain="sync")
sim.add_testbench(testbench)