Ethernet: add 3.3R MDI dampers (R32-R35) and J2 center-tap bypass (C20/C21)

Completes the WIZnet reference schematic for the MDI section:
- R32-R35 3.3R 1% (YAGEO RC0402FR-073R3L, LCSC C137986) in series in
  each MDI line per WIZnet note 6 (EMI damping). Chain per line is now
  U11 pin -> 49.9R termination tap -> 3.3R -> D4/D5 flow-through -> J2.
  Chip-side nets keep PHY_*; the D4/D5-side segments are renamed MDI_*
  and added to the ETH_DP netclass patterns so the impedance DRC rules
  police both halves.
- C20 100nF (C1525) + C21 1uF (C15849) on ETH_3V3 per WIZnet note 7 -
  to be placed AT J2 pins 4/5 tapping the In2 ETH_3V3 island.

(Also carries KiCad's resave/reposition of ethernet.kicad_sch from the
rework session - netlist-identical, verified.)

Verified: ERC 0, netlist 121 components vs BOM 120 (J3-only delta),
PHY_TX_P = {U11.3, R26.1, R32.1}, MDI_TX_P = {R32.2, D4.1}, and
likewise for all four lines. PCB: 6 footprints to place (cut the lines
between termination and D4/D5 for R32-R35; C20/C21 at the jack).

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>

hardware/re-bba-rb/TODO.md

@@ -29,16 +29,26 @@ W5100S reference schematic, and JLCPCB manufacturing limits. ERC/DRC: clean.
       part DONE 2026-07-17: added R26/R27 (49.9 Ω 1%, LCSC C25120) from
       TXOP/TXON to a common node + C18 (100 nF) to GND, and R28/R29 + C19 for
       RXIP/RXIN, on the PHY-side nets per the WIZnet reference schematic.
-      ERC 0; netlist verified. Remaining (PCB rework):
-      - [ ] Place the 6 new footprints (Update PCB from Schematic / F8 pulls
-            them in) **next to U11 pins 2/3/5/6** — WIZnet: "place the 49.9
-            resistors and 0.1uF capacitor near the MDI pin of W5100S".
-      - [ ] Keep the pair stubs to the resistors short; the ETH_DP netclass
-            width/gap rules still apply to the through-line.
-      - [ ] Optional (left out deliberately): 3.3 Ω series damping resistors
-            in each line (WIZnet note 6, EMI reduction) — would require
-            breaking the pairs; add only if EMI testing demands.
-      - [ ] Place C51/C52 physically at J2 pins 4/5 (center taps).
+      ERC 0; netlist verified. PCB rework REVIEWED 2026-07-18 — PASS:
+      - [x] Termination placed at U11's MDI edge (R26–R29 ~1–3 mm from pins,
+            C18/C19 2.8 mm from their resistor pairs); stubs short; DRC 0
+            errors incl. ETH_DP impedance rules; pair skew TX 0.30 mm /
+            RX 0.72 mm; pairs on F.Cu over solid In1 GND (one short B.Cu
+            crossover via per N line at the jack — fine).
+      - [x] D4/D5 flow-through verified pad-by-pad (PHY side faces U11,
+            cable side faces J2); In1 plane correctly voided under the
+            magjack's cable/isolation side, all layers clear there.
+      - [ ] 3.3 Ω series dampers (WIZnet note 6) — schematic ADDED
+            2026-07-18: R32–R35 (YAGEO RC0402FR-073R3L, LCSC C137986) in
+            line U11→transformer; chip-side nets stay PHY_*, D4/D5-side
+            renamed MDI_* (netclass patterns added to ETH_DP in .kicad_pro
+            so the impedance rules still police both halves). PCB: cut the
+            four lines between the termination cluster and D4/D5 and insert
+            the footprints there (F8 pulls them + the MDI_* pad renames).
+      - [ ] Center-tap bypass (WIZnet note 7) — schematic ADDED 2026-07-18:
+            C20 100 nF (C1525) + C21 1 µF 0603 (C15849) on ETH_3V3. PCB:
+            place BOTH right at J2 pins 4/5, tapping the In2 ETH_3V3 island
+            with short traces + local GND vias.
       - [x] D4/D5 (USBLC6 on the PHY pairs) — RESOLVED 2026-07-17: **keep,
             exactly as drawn.** ST explicitly rates USBLC6 for Ethernet;
             PHY-side placement guards residual coupling through the

hardware/re-bba-rb/re-bba-rb.kicad_pro

@@ -664,6 +664,22 @@
         "netclass": "ETH_DP",
         "pattern": "*ETH_RX_N*"
       },
+      {
+        "netclass": "ETH_DP",
+        "pattern": "*MDI_TX_P*"
+      },
+      {
+        "netclass": "ETH_DP",
+        "pattern": "*MDI_TX_N*"
+      },
+      {
+        "netclass": "ETH_DP",
+        "pattern": "*MDI_RX_P*"
+      },
+      {
+        "netclass": "ETH_DP",
+        "pattern": "*MDI_RX_N*"
+      },
       {
         "netclass": "ETH_DP",
         "pattern": "*PHY_TX_P*"