From bad2b54574824d0f6beee1dbeaf1a7b7a6209eb1 Mon Sep 17 00:00:00 2001 From: Dennis Brentjes Date: Sat, 18 Jul 2026 14:14:01 +0000 Subject: [PATCH] TODO: verify and update status - all critical findings resolved Re-verified every open item against the current board: - All three critical findings (DO/DI swap, MDI termination incl. dampers + center-tap bypass, FTDI EEPROM resistors) now done in both schematic and PCB - marked resolved with review results - Marked verified-done: 12V cap ratings, 1% tolerances, .history ignore, fiducial check (absent - to add with debug pass) - Confirmed still open: ETH_RST pull-up, PR1 divider margin (R3 still 200k), RSET 12.4k vs 12.3k, TPS22810 CT, iceprog pin mapping, board PCF, debug LEDs/test points, mechanical fit, ordering options Co-Authored-By: Claude Fable 5 --- hardware/re-bba-rb/TODO.md | 65 +++++++++++++++++++------------------- 1 file changed, 33 insertions(+), 32 deletions(-) diff --git a/hardware/re-bba-rb/TODO.md b/hardware/re-bba-rb/TODO.md index 8d94149..cd7d9c9 100644 --- a/hardware/re-bba-rb/TODO.md +++ b/hardware/re-bba-rb/TODO.md @@ -1,10 +1,12 @@ # re-bba-rb board — open items from hardware review (2026-07-17) -Full review of schematics + PCB against component datasheets -(`datasheets/` — restore from commit `db457a0`, see Housekeeping), the WIZnet -W5100S reference schematic, and JLCPCB manufacturing limits. ERC/DRC: clean. +Full review of schematics + PCB against component datasheets (in +`datasheets/`), the WIZnet W5100S reference schematic, and JLCPCB +manufacturing limits. Status 2026-07-18: **all three critical findings fixed +in schematic AND PCB** (ERC 0, DRC 0 errors / 0 unconnected / 0 parity); +remaining work is the Functional/Broader/ordering lists below. -## Critical — must fix before (or with) next fab +## Critical — ALL RESOLVED (schematic + PCB, verified 2026-07-18) - [x] **EXI DO/DI swapped at J3 — FIXED 2026-07-17** (all copper unchanged). YAGCD SP1 naming is console-perspective: pin 6 `DO` = GC data **out** → @@ -25,8 +27,8 @@ W5100S reference schematic, and JLCPCB manufacturing limits. ERC/DRC: clean. - [ ] Use this final pin map when writing the board PCF (see Broader items): MOSI = pin 4, MISO = pin 3, CLK = 44 (G6), CS = 45, INT = 46. -- [ ] **W5100S MDI termination network** (`ethernet.kicad_sch`) — schematic - part DONE 2026-07-17: added R26/R27 (49.9 Ω 1%, LCSC C25120) from +- [x] **W5100S MDI termination network — DONE (schematic + PCB)**: added + R26/R27 (49.9 Ω 1%, LCSC C25120) from TXOP/TXON to a common node + C18 (100 nF) to GND, and R28/R29 + C19 for RXIP/RXIN, on the PHY-side nets per the WIZnet reference schematic. ERC 0; netlist verified. PCB rework REVIEWED 2026-07-18 — PASS: @@ -38,17 +40,16 @@ W5100S reference schematic, and JLCPCB manufacturing limits. ERC/DRC: clean. - [x] D4/D5 flow-through verified pad-by-pad (PHY side faces U11, cable side faces J2); In1 plane correctly voided under the magjack's cable/isolation side, all layers clear there. - - [ ] 3.3 Ω series dampers (WIZnet note 6) — schematic ADDED - 2026-07-18: R32–R35 (YAGEO RC0402FR-073R3L, LCSC C137986) in - line U11→transformer; chip-side nets stay PHY_*, D4/D5-side - renamed MDI_* (netclass patterns added to ETH_DP in .kicad_pro - so the impedance rules still police both halves). PCB: cut the - four lines between the termination cluster and D4/D5 and insert - the footprints there (F8 pulls them + the MDI_* pad renames). - - [ ] Center-tap bypass (WIZnet note 7) — schematic ADDED 2026-07-18: - C20 100 nF (C1525) + C21 1 µF 0603 (C15849) on ETH_3V3. PCB: - place BOTH right at J2 pins 4/5, tapping the In2 ETH_3V3 island - with short traces + local GND vias. + - [x] 3.3 Ω series dampers (WIZnet note 6) — DONE 2026-07-18: R32–R35 + (YAGEO RC0402FR-073R3L, LCSC C137986) in line U11→transformer; + chip-side nets stay PHY_*, D4/D5-side renamed MDI_* (patterns + added to ETH_DP netclass in .kicad_pro). Inserted in-line on the + PCB, each in its own line row; MDI_* stubs 1.45–1.48 mm, no new + vias; pair skew after insertion TX 0.66 mm / RX 1.81 mm (fine). + - [x] Center-tap bypass (WIZnet note 7) — DONE 2026-07-18: C20 100 nF + (C1525) + C21 1 µF 0603 (C15849) on ETH_3V3, placed against + J2's pin column — as close to pins 4/5 as the In1 plane void + allows while keeping short GND vias. - [x] D4/D5 (USBLC6 on the PHY pairs) — RESOLVED 2026-07-17: **keep, exactly as drawn.** ST explicitly rates USBLC6 for Ethernet; PHY-side placement guards residual coupling through the @@ -63,14 +64,11 @@ W5100S reference schematic, and JLCPCB manufacturing limits. ERC/DRC: clean. stub (stub inductance adds L·di/dt let-through). Layout: route the pair in-line through the package, near J2, short GND via on pin 2. If ever bypassing at bring-up: desolder + jumper 1–6/3–4. -- [ ] **FT2232H EEPROM interface** (`Usb Connector.kicad_sch`) — schematic - part DONE 2026-07-17 per datasheet Table 3.4: U7.4 (DO) moved to new - net EE_DO; R30 (2.2 kΩ, C25879) inserted EE_DO→EE_DATA; R31 (10 kΩ, - C25744) pull-up EE_DO→3V3. EEDATA→DI stays direct. ERC 0, netlist - verified, BOM fields populated. Remaining (PCB rework): - - [ ] Place/route R30 + R31 near U7 (Update PCB from Schematic pulls - them in together with the 6 MDI termination parts — 8 new - footprints total). +- [x] **FT2232H EEPROM interface — DONE (schematic + PCB)** per datasheet + Table 3.4: U7.4 (DO) moved to new net EE_DO; R30 (2.2 kΩ, C25879) + inserted EE_DO→EE_DATA; R31 (10 kΩ, C25744) pull-up EE_DO→3V3. + EEDATA→DI stays direct. R30/R31 placed 4–5 mm from U7, routed, DRC + parity 0. ERC 0, netlist verified, BOM fields populated. ## Functional / robustness @@ -131,8 +129,8 @@ W5100S reference schematic, and JLCPCB manufacturing limits. ERC/DRC: clean. iceprog-pin-mapping decision above (changes the schematic). - [ ] CC1/CC2 have no ESD protection (USBLC6 covers D+/D− only) — optional, most hobby designs skip; note spare-channel budget if respinning D2 area. -- [ ] Ensure `hardware/re-bba-rb/.history/` (contains an embedded `.git`) is - gitignored and never committed. +- [x] `.history/` (embedded `.git`) — VERIFIED ignored via root + `.gitignore:28`, nothing tracked. ## Minor / BOM @@ -142,10 +140,10 @@ W5100S reference schematic, and JLCPCB manufacturing limits. ERC/DRC: clean. (Y1 YXC X322512MOB4SI / C70565, Y2 X322525MOB4SI / C9006, both JLC Basic, ±10 ppm) — correct for the 18 pF load caps and the W5100S Table 9 recommendation. No change needed. -- [ ] 12 V-rail parts ≥ 25 V rating: C3, C4 (10 µF 0805), C6, C65 (100 µF - electrolytic); D3 SMAJ12A already correct. -- [ ] 1 % tolerance required: R1/R2 (buck VFB divider, TI requirement), - R10 (FTDI REF 12 k), R16 (RSET_BG), R3/R4 (PR1 divider). +- [x] 12 V-rail parts ≥ 25 V — VERIFIED in BOM audit 2026-07-17: C3/C4 25 V, + C6 50 V, C65 25 V (Lelon SMD electrolytic); D3 SMAJ12A correct. +- [x] 1 % tolerance — VERIFIED in BOM audit 2026-07-17: R1/R2, R3/R4, R10, + R16 are all 1 % UNI-ROYAL parts (and new R26–R35 are 1 %). - [ ] TPS22810 CT: floating = fastest ramp (~0.7 A inrush into ETH rail caps). Consider CT = 10 nF footprint (DNP-able). - [ ] Verify HR911105A internal LED pinout (assumed: 9/12 anodes via @@ -173,7 +171,10 @@ W5100S reference schematic, and JLCPCB manufacturing limits. ERC/DRC: clean. pin-compatible, but treat as a bring-up suspect if EXI ESD behaviour looks odd. C65 is an SMD electrolytic (Lelon VZH101M1ETR-0607, 25 V) — assembly-friendly, not THT as first assumed. -- [ ] Check fiducials for SMT assembly. +- [ ] Fiducials: VERIFIED ABSENT (0 on the board, 2026-07-18). JLCPCB can + panel-add their own, but 3 board fiducials (1 mm copper dot, 2 mm mask + opening, asymmetric corners) is the robust choice — add with the debug + LEDs/test points pass. ## Housekeeping (repo) — done 2026-07-17