From c0c123e88b76ef2ef0b46a27996c38fd4aa60d22 Mon Sep 17 00:00:00 2001 From: Dennis Brentjes Date: Wed, 2 Sep 2026 21:34:17 +0200 Subject: [PATCH] Fixes the GC/USB power led handover --- hardware/re-bba-rb/BRINGUP.md | 36 +++++++++++++++++--------- hardware/re-bba-rb/Power.kicad_sch | 18 ++++++------- hardware/re-bba-rb/REVIEW.md | 9 +++++++ hardware/re-bba-rb/TODO.md | 34 ++++++++++++------------ hardware/re-bba-rb/re-bba-rb.kicad_pcb | 12 ++++----- 5 files changed, 64 insertions(+), 45 deletions(-) diff --git a/hardware/re-bba-rb/BRINGUP.md b/hardware/re-bba-rb/BRINGUP.md index 63e0609..92818ba 100644 --- a/hardware/re-bba-rb/BRINGUP.md +++ b/hardware/re-bba-rb/BRINGUP.md @@ -69,7 +69,7 @@ the impedance-matching resistors — wrong part for an LED.) The RGB LED part of this complaint. BOM/PCB change for V2; a rework could tack larger resistors on this unit if the brightness is a bench nuisance. -### 2. GC_ON is not the clean on/off the gateware assumed (sits at 2.3 V; both handover LEDs on) +### 2. GC_ON was not a clean on/off (sat at 2.3 V; both handover LEDs on) — FIXED in schematic 2026-08-28 **Observation:** `GC_ON` measures **2.3 V** (not a clean rail). With **both USB and GC connected**, both transistor-driven LEDs (D8, D9) are lit — the intent @@ -83,17 +83,29 @@ U12.3, FPGA **U9 pin 21**, pulled up by R5 10 k to 3V3; drives Q1 base via R39 when base ≲2.6 V) **both conduct** → both D8 and D9 light. There is no clean one-or-the-other point at this intermediate voltage. -**Two things to resolve:** -- **Hardware:** the complementary-transistor indicator doesn't give a clean - handover display at the actual GC_ON level. Re-think for V2 (e.g., a comparator - / proper level, or drive the two indicators from a real one-hot power-source - signal). First confirm what GC_ON's ST pin actually does across the USB-only / - GC-only / both states (TPS2116 ST semantics — see REVIEW.md). -- **Gateware:** GC_ON is wired to FPGA pin 21 but **not yet used**. The planned - "gate all outputs on GC_ON" (see TODO.md) assumed GC_ON is a clean logic level. - 2.3 V is above the iCE40 3.3 V-LVCMOS V_IH (~2.0 V) so pin 21 would read HIGH, - but it's marginal and the semantics aren't the assumed on/off. Verify the real - signal before relying on it for output gating. +**Root cause (identified 2026-08-28):** the intermediate ~2.3 V is **base-loading +of the open-drain ST node**. When GC is the source, ST is Hi-Z and *should* sit at +3V3 (R5 pull-up), but Q1's base (through R39 10 k) drags it down — R5‖R39 divide +3V3 to ~2.0 V — which is low enough that the PNP Q2's V_EB ≈ 1.3 V and it conducts +too. So both LEDs light, and the FPGA/EN see a soggy 2 V instead of 3V3. +TPS2116 ST is only characterised to sink **1 mA** (DS: V_OL @ I_ST = 1 mA, +t_ST @ R_ST = 10 k), so simply strengthening R5 is not allowed. + +**Hardware fix — APPLIED 2026-08-28 (schematic):** raise the base resistors and +modestly lower the pull-up so GC_ON swings clean while ST stays ≤1 mA: +- **R5 10 k → 5.1 k** (C25905, reuses R6/R7 part) +- **R39 / R40 10 k → 33 k** (C25779, reuses R1 part) +Result: GC active → GC_ON ≈ **2.95 V** → Q1 saturates (D8/GC lit), Q2 V_EB ≈ +0.35 V → OFF (D9/USB dark); USB active → ST low (sinks ~0.73 mA < 1 mA) → D9 lit, +D8 dark. Clean one-hot. **No new BOM lines, no PCB layout change** (resistor value +swaps only — run "Update PCB from Schematic" so the F.Fab values match). This also +**resolves the gateware concern below**: GC_ON now reads a solid ~2.95 V (well +above the iCE40 V_IH) instead of a marginal 2.3 V. D8/D9 = GC/USB is the confirmed +assignment (TPS2116 ST "low when VIN1 not used", VIN1 = GC priority — see +REVIEW.md); the B.SilkS labels are correct. +- ~~**Gateware:** GC_ON marginal at 2.3 V for the FPGA pin-21 read~~ — addressed + by the fix above (now ~2.95 V). The "gate all outputs on GC_ON" work (TODO) + can now assume a clean level; still verify on the reworked bench unit. ### 3. Functional W5100 test — send a packet capturable in Wireshark (works around broken D3?) diff --git a/hardware/re-bba-rb/Power.kicad_sch b/hardware/re-bba-rb/Power.kicad_sch index 563f44c..c211c56 100644 --- a/hardware/re-bba-rb/Power.kicad_sch +++ b/hardware/re-bba-rb/Power.kicad_sch @@ -5314,7 +5314,7 @@ (justify left) ) ) - (property "Value" "10k" + (property "Value" "33k" (at 62.23 61.15 0) (show_name no) (do_not_autoplace no) @@ -5358,7 +5358,7 @@ ) ) ) - (property "MPN" "0402WGF1002TCE" + (property "MPN" "0402WGF3302TCE" (at 62.23 57.15 0) (hide yes) (show_name no) @@ -5369,7 +5369,7 @@ ) ) ) - (property "LCSC" "C25744" + (property "LCSC" "C25779" (at 62.23 57.15 0) (hide yes) (show_name no) @@ -7314,7 +7314,7 @@ (justify left) ) ) - (property "Value" "10k" + (property "Value" "5.1k" (at 132.08 44.45 0) (show_name no) (do_not_autoplace no) @@ -7358,7 +7358,7 @@ ) ) ) - (property "MPN" "0402WGF1002TCE" + (property "MPN" "0402WGF5101TCE" (at 0 0 0) (hide yes) (show_name no) @@ -7380,7 +7380,7 @@ ) ) ) - (property "LCSC" "C25744" + (property "LCSC" "C25905" (at 0 0 0) (hide yes) (show_name no) @@ -8143,7 +8143,7 @@ (justify left) ) ) - (property "Value" "10k" + (property "Value" "33k" (at 17.78 72.58 0) (show_name no) (do_not_autoplace no) @@ -8187,7 +8187,7 @@ ) ) ) - (property "MPN" "0402WGF1002TCE" + (property "MPN" "0402WGF3302TCE" (at 17.78 68.58 0) (hide yes) (show_name no) @@ -8198,7 +8198,7 @@ ) ) ) - (property "LCSC" "C25744" + (property "LCSC" "C25779" (at 17.78 68.58 0) (hide yes) (show_name no) diff --git a/hardware/re-bba-rb/REVIEW.md b/hardware/re-bba-rb/REVIEW.md index a6631f9..925cdd7 100644 --- a/hardware/re-bba-rb/REVIEW.md +++ b/hardware/re-bba-rb/REVIEW.md @@ -42,6 +42,15 @@ datasheet extraction, WebSearch/WebFetch for parts and reference designs. FPGA-GC_ON use. USB-only fallback verified via truth table (MODE≤0.35 V row). PR1 divider was marginal (1.10 V vs VREF 1.0±8 %) → **fixed: R3=150k** (switchover 2.30–2.70 V). Abs max (6 V) fine. + **D8/D9 handover-indicator base-loading fixed 2026-08-28:** the complementary + Q1(NPN)/Q2(PNP) indicator bases hung on the open-drain ST/GC_ON node through + R39/R40 10 k; with R5 10 k they divided GC_ON to ~2 V on GC power, turning BOTH + LEDs on and giving the FPGA/EN a soggy level (BRINGUP #2). ST is only + characterised to 1 mA sink, so R5 can't just be strengthened. Fix: **R5 10k→5.1k + (C25905), R39/R40 10k→33k (C25779)** → GC_ON ≈ 2.95 V on GC (Q1 sat / Q2 off, + D8=GC only), ST sinks ~0.73 mA on USB (Q2 on, D9=USB only). Clean one-hot; + reuses existing parts; no PCB layout change. D8=GC / D9=USB assignment confirmed + (ST low when VIN1 not used, VIN1=GC priority). - **AP2112K-1.2 (U1) / AP2112K-3.3 (U4)**: 1 µF X5R in/out present (DS requirement), 600 mA rating vs load fine, dropout headroom checked (1.2 V version has 1.0–1.3 V dropout — OK from 3.3 V), EN=VIN OK. diff --git a/hardware/re-bba-rb/TODO.md b/hardware/re-bba-rb/TODO.md index 96d805f..b92f671 100644 --- a/hardware/re-bba-rb/TODO.md +++ b/hardware/re-bba-rb/TODO.md @@ -143,24 +143,22 @@ Cosmetic/mechanical items for the in-progress V2 rework (EEPROM→93LC56B, reverse-mount LEDs, J3 slot already done). These are PCB-layout tasks, not schematic changes. -- [ ] **1. Add the project name in silkscreen.** Put a "re-bba-rb" (or chosen - project name/version) label on the board silkscreen so the assembled board - is identifiable. Pick a copper-free spot; watch the JLC 1.0 mm min text - height / 0.15 mm min line-width floor (same rule that just caught the LED - refdes). Consider adding a small rev tag (e.g. "v2") next to it. -- [ ] **2. Extend the board out to the ethernet socket so it sits flush with the - GC.** Lengthen the board outline (Edge.Cuts) toward the RJ45/magjack (J2) - end so the finished board reaches flush with the GameCube's shell instead - of stopping short. Mechanical-only (move the board edge + any ground pour - to suit); keep the SP1/J3 edge geometry fixed. Verify the new outline - against the GC slot depth before ordering. -- [ ] **3. Add back-side silkscreen legends for the LEDs.** Label what each LED - means on **B.SilkS** (the back is the viewing side — reverse-mount LEDs - emit through the board, top faces into the GC slot). Map from the current - build: LEDG/D6 = heartbeat, LEDR/D7 = EXI activity, RGB D11 = rx / D12 = - tx / D13 = ready, D8/D9 = USB/GC power handover indicators. Confirm the - final per-LED meaning against `synth.py` + BRINGUP.md before lettering, and - mind the same silk text-height/width floor as item 1. +- [x] **1. Add the project name in silkscreen — DONE 2026-08-28** (commit + "Added Silkscreen labels"). "ReBBArb V2" (2 mm) on B.SilkS, mid-board. + Free-floating over some copper (silk_over_copper warning, JLC clips it) — + reposition to taste if wanted. +- [ ] ~~**2. Extend the board to the ethernet socket for a flush GC fit.**~~ + **DROPPED 2026-08-28** — Dennis decided against extending the outline; + board ships at its current length. +- [x] **3. Back-side silkscreen LED legends — DONE 2026-08-28** (same commit). + On B.SilkS (mirrored): RX (D11) / TX (D12) / RDY (D13) / HB (D6, heartbeat) + / EXI (D7) as vertical labels above the LED-window row; USB (D9) / GC (D8) + above the two power LEDs. Semantics confirmed against `synth.py`. + D8/D9 = GC/USB assignment **confirmed** (TPS2116 ST low when VIN1 not used, + VIN1 = GC priority) and the handover indicator **circuit fixed** 2026-08-28 + (R5 10k→5.1k, R39/R40 10k→33k — see BRINGUP #2 / REVIEW.md), so the labels + are correct and the indicator is now clean one-hot. "ReBBArb V2" name + position confirmed fine by Dennis. ## Critical — ALL RESOLVED (schematic + PCB, verified 2026-07-18) diff --git a/hardware/re-bba-rb/re-bba-rb.kicad_pcb b/hardware/re-bba-rb/re-bba-rb.kicad_pcb index 2817c83..9654a12 100644 --- a/hardware/re-bba-rb/re-bba-rb.kicad_pcb +++ b/hardware/re-bba-rb/re-bba-rb.kicad_pcb @@ -3603,7 +3603,7 @@ ) ) ) - (property "Value" "10k" + (property "Value" "33k" (at 0 1.17 90) (layer "F.Fab") (uuid "660266f2-d8cd-4e63-bc1a-418e418c2d76") @@ -3661,7 +3661,7 @@ ) ) ) - (property "LCSC" "C25744" + (property "LCSC" "C25779" (at 0 0 90) (unlocked yes) (layer "F.Fab") @@ -17797,7 +17797,7 @@ ) ) ) - (property "Value" "10k" + (property "Value" "5.1k" (at 0 1.17 90) (layer "F.Fab") (uuid "ccf842e5-1b0d-43e6-981b-8fb93f841dfa") @@ -17869,7 +17869,7 @@ ) ) ) - (property "LCSC" "C25744" + (property "LCSC" "C25905" (at 0 0 270) (unlocked yes) (layer "F.Fab") @@ -23573,7 +23573,7 @@ ) ) ) - (property "Value" "10k" + (property "Value" "33k" (at 0 1.17 90) (layer "F.Fab") (uuid "7696d858-4c8e-46b2-97a0-f6d71e0d1f1b") @@ -23631,7 +23631,7 @@ ) ) ) - (property "LCSC" "C25744" + (property "LCSC" "C25779" (at 0 0 90) (unlocked yes) (layer "F.Fab")