Add integrated UART UDP bring-up shell (socket 3) + capture critical-path fix
An interactive UART command shell drives a UDP send/receive test on the W5100's socket 3, running ALONGSIDE the live BBA (socket-0 MACRAW) with EXI keeping bus priority. MACRAW+UDP coexistence is W5100S-datasheet confirmed (S4.6 + "4 independent SOCKETs"). Now the default flash build (--console selects the old event-log console). New / changed gateware: - uart_shell.py (new): rebbarb> shell over FT2232H channel B. Commands: help; udp unicast <ip> [msg]; udp broadcast [msg]. After each send it waits (bounded, else "timeout") for a reply and prints "rx <payload>". Line buffer + message ROM live in block RAM with a sequential parser (LC-efficient); 1-deep RX holding reg keeps pastes intact. 8 sim tests. - w5100_parallel_master.py: configurable UDP socket (default 3) with UDP send AND receive (IP-stack init, runtime dest IP, WIZnet UDP RX header + payload). Gated by enable_udp_test so the MACRAW path is unchanged when off. Tests U1-U4 + MACRAW T1-T5. - exi_capture.py: CAPTURE-DOMAIN CRITICAL-PATH FIX. The TX byte-FIFO read-enable was gated by its own gray-coded ready (r_en = ... | (flushing & r_rdy)), forming a consume_ptr -> gray -> r_rdy -> flush -> r_en -> consume_ptr loop that capped capture_clk. Replaced the r_rdy-based "drain until empty" flush with a fixed-length drain counter (FIFO is only tx_depth deep), removing the pointer feedback from r_en. Path 24.3 -> 19.6 ns; flush behavior preserved. - bba_top.py: wire shell <-> W5100 UDP (send + rx); shell additive. - synth.py: shell default build; env-var UDP network config; documents a reverted PNR-timing-priority experiment. Timing (--seeds 8, default shell build, 67% LC): capture closes on 4/8 seeds (best seed 4 = 58.36 MHz, +8%), clk passes on all. This is BETTER than the pre-shell 2/8 baseline because the flush fix improved the capture domain intrinsically. Flash build/seed4/top.bin. Bring-up caveats (unchanged): W5100 socket register addresses / UDP header format are datasheet-derived (confirm on hardware); UDP_SRC_IP / subnet / gateway must match the LAN for unicast ARP. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
This commit is contained in:
@@ -45,7 +45,10 @@ __all__ = ["W5100ParallelMaster"]
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# ── W5100 register addresses (indirect 16-bit address space) ────────────────
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_MR = 0x0000 # Mode register (common)
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_GAR0 = 0x0001 # Gateway IP, 4 bytes
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_SUBR0 = 0x0005 # Subnet mask, 4 bytes
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_SHAR0 = 0x0009 # Source MAC, 6 bytes
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_SIPR0 = 0x000F # Source IP, 4 bytes
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_IR = 0x0015 # Interrupt register
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_IMR = 0x0016 # Interrupt mask
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_RMSR = 0x001A # RX memory size (2 bits/socket)
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@@ -60,20 +63,50 @@ _S0_TX_WR = 0x0424 # Socket 0 TX write pointer
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_S0_RX_RSR = 0x0426 # Socket 0 RX received size (2 bytes)
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_S0_RX_RD = 0x0428 # Socket 0 RX read pointer
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# Per-socket register/buffer geometry (2 KB per socket, RMSR/TMSR=0x55).
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# The UDP-test socket number is configurable; addresses are computed from it in
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# __init__ (see _socket_addrs). Socket-n register block base = 0x0400+n*0x100,
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# TX buffer base = 0x4000+n*0x800, RX buffer base = 0x6000+n*0x800.
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_TX_BASE = 0x4000 # Socket 0 TX buffer base (default 2 KB window)
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_RX_BASE = 0x6000 # Socket 0 RX buffer base
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_S0_TX_MASK = 0x07FF # 2 KB ring mask
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_S0_RX_MASK = 0x07FF
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_SN_MASK = 0x07FF # 2 KB ring mask (any socket)
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def _socket_addrs(n):
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"""Return the register/buffer addresses for socket `n` (0..3)."""
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base = 0x0400 + n * 0x0100
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return dict(
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MR=base + 0x00, CR=base + 0x01, IR=base + 0x02, SR=base + 0x03,
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PORT=base + 0x04, DIPR=base + 0x0C, DPORT=base + 0x10,
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TX_WR=base + 0x24, RX_RSR=base + 0x26, RX_RD=base + 0x28,
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TX_BASE=0x4000 + n * 0x0800, RX_BASE=0x6000 + n * 0x0800,
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)
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# MR bits / command / mode values
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_MR_RST = 0x80
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_MR_AI = 0x02 # address auto-increment (indirect mode)
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_MR_IND = 0x01 # indirect bus interface mode
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_S0_MR_MACRAW = 0x04
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_S1_MR_UDP = 0x02 # socket UDP mode
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_CR_OPEN = 0x01
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_CR_SEND = 0x20
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_CR_RECV = 0x40
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def _ip_bytes(dotted):
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"""'192.168.1.100' → [192, 168, 1, 100] (big-endian, network order)."""
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parts = [int(x) for x in dotted.split(".")]
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if len(parts) != 4 or any(not 0 <= p <= 255 for p in parts):
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raise ValueError(f"invalid IPv4 address: {dotted!r}")
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return parts
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def _port_bytes(port):
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"""6464 → [0x19, 0x40] (big-endian)."""
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return [(port >> 8) & 0xFF, port & 0xFF]
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# Indirect-mode address selects (A[1:0])
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_A_MR = 0b00
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_A_AR0 = 0b01 # IDM_AR high byte
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@@ -97,12 +130,64 @@ class W5100ParallelMaster(Elaboratable):
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Init / TX / RX interfaces are identical to W5500SPIMaster.
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"""
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def __init__(self, strobe_cycles=3, reset_cycles=24000):
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def __init__(self, strobe_cycles=3, reset_cycles=24000,
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enable_udp_test=False, udp_socket=3,
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src_ip="192.168.1.123", subnet="255.255.255.0",
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gateway="192.168.1.1", dst_ip="192.168.1.100",
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src_port=6464, dst_port=6464,
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udp_payload=b"REBBARB-UDP-TEST\r\n"):
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# /RD//WR strobe width in sync cycles (≥ W5100 access time).
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self._strobe = strobe_cycles
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# MR-reset settle wait; testbench overrides with a small value.
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self._reset_cycles = reset_cycles
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# ── Optional socket-1 UDP bring-up test ───────────────────────────────
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# When enabled, init also configures the W5100's IP stack (GAR/SUBR/
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# SIPR) and opens socket 1 in UDP mode; pulsing `udp_send_req` then
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# emits one UDP datagram to `udp_dst_ip`:dst_port with the payload
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# supplied on the `udp_pl_*` stream. MACRAW socket 0 is untouched.
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# Everything below is elaborated only when enabled, so a plain BBA
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# build (and the existing MACRAW testbench) is bit-for-bit unchanged.
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#
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# Network config is build-time (the board's own address); the
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# destination and payload are RUNTIME so the UART shell can drive them
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# from a typed command. `dst_ip` here is only a power-on default for
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# the udp_dst_ip input.
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if not 1 <= udp_socket <= 3:
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raise ValueError("udp_socket must be 1..3 (socket 0 is MACRAW)")
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self._enable_udp = enable_udp_test
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self._sn = _socket_addrs(udp_socket)
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self._src_ip = _ip_bytes(src_ip)
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self._subnet = _ip_bytes(subnet)
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self._gateway = _ip_bytes(gateway)
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self._src_port = _port_bytes(src_port)
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self._dst_port = _port_bytes(dst_port)
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_dst_default = _ip_bytes(dst_ip)
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# Runtime UDP-send control / datapath.
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self.udp_send_req = Signal() # pulse: emit one datagram
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self.udp_test_busy = Signal() # level: send in progress
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self.udp_dst_ip = Signal(32, # destination IP (big-endian:
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init=int.from_bytes(bytes(_dst_default), "big")) # [0]=MSB octet)
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# Payload byte stream (driven by the shell; consumed during the send).
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self.udp_pl_data = Signal(8)
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self.udp_pl_valid = Signal()
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self.udp_pl_last = Signal()
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self.udp_pl_ready = Signal()
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# UDP receive (poll-driven): pulse udp_rx_req to check the socket's RX
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# buffer for a datagram. Either udp_rx_none pulses (nothing waiting) or
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# the payload streams out on udp_rx_* (sof/eof frame the datagram);
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# udp_rx_busy is high while a check/read is in progress.
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self.udp_rx_req = Signal()
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self.udp_rx_busy = Signal()
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self.udp_rx_none = Signal()
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self.udp_rx_data = Signal(8)
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self.udp_rx_valid = Signal()
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self.udp_rx_sof = Signal()
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self.udp_rx_eof = Signal()
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self.udp_rx_ready = Signal()
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# Physical parallel bus
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self.bus_addr = Signal(2)
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self.bus_data_o = Signal(8)
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@@ -136,6 +221,7 @@ class W5100ParallelMaster(Elaboratable):
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def elaborate(self, platform):
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m = Module()
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STROBE = self._strobe
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sn = self._sn # UDP-test socket register/buffer addresses
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# ── Bus access engine: one indirect-bus read or write cycle ──────────
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bus_go = Signal()
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@@ -209,13 +295,43 @@ class W5100ParallelMaster(Elaboratable):
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s_data, s_valid, s_last, s_consume = Signal(8), Signal(), Signal(), Signal()
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r_data, r_valid, r_first, r_last, r_ready = (
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Signal(8), Signal(), Signal(), Signal(), Signal())
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# TX stream source = external tx interface (Phase 2).
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m.d.comb += [s_data.eq(self.tx_data), s_valid.eq(self.tx_valid),
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s_last.eq(self.tx_eof), self.tx_ready.eq(s_consume)]
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# RX stream sink = external rx interface (Phase 3).
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m.d.comb += [self.rx_data.eq(r_data), self.rx_valid.eq(r_valid),
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self.rx_sof.eq(r_first), self.rx_eof.eq(r_last),
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r_ready.eq(self.rx_ready)]
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# TX stream-write source mux: during a UDP-test send the payload comes
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# from the external `udp_pl_*` stream (the shell); otherwise the normal
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# MACRAW TX interface feeds it. `udp_streaming` is raised only while the
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# UDP payload is being written to the socket-1 TX buffer.
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udp_streaming = Signal()
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if self._enable_udp:
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with m.If(udp_streaming):
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m.d.comb += [s_data.eq(self.udp_pl_data),
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s_valid.eq(self.udp_pl_valid),
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s_last.eq(self.udp_pl_last),
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self.udp_pl_ready.eq(s_consume)]
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with m.Else():
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m.d.comb += [s_data.eq(self.tx_data), s_valid.eq(self.tx_valid),
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s_last.eq(self.tx_eof), self.tx_ready.eq(s_consume)]
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else:
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m.d.comb += [s_data.eq(self.tx_data), s_valid.eq(self.tx_valid),
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s_last.eq(self.tx_eof), self.tx_ready.eq(s_consume)]
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# RX stream-read sink mux: during a socket-N UDP receive the payload
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# streams out on `udp_rx_*` (to the shell); otherwise it goes to the
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# MACRAW rx interface (to the frame assembler). `udp_rx_streaming` is
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# raised only while the UDP payload is being read out.
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udp_rx_streaming = Signal()
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if self._enable_udp:
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with m.If(udp_rx_streaming):
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m.d.comb += [self.udp_rx_data.eq(r_data),
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self.udp_rx_valid.eq(r_valid),
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self.udp_rx_sof.eq(r_first),
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self.udp_rx_eof.eq(r_last),
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r_ready.eq(self.udp_rx_ready)]
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with m.Else():
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m.d.comb += [self.rx_data.eq(r_data), self.rx_valid.eq(r_valid),
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self.rx_sof.eq(r_first), self.rx_eof.eq(r_last),
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r_ready.eq(self.rx_ready)]
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else:
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m.d.comb += [self.rx_data.eq(r_data), self.rx_valid.eq(r_valid),
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self.rx_sof.eq(r_first), self.rx_eof.eq(r_last),
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r_ready.eq(self.rx_ready)]
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# Socket-buffer ring wraparound. Unlike the W5500, the W5100's IDM
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# address does NOT auto-wrap at the socket-buffer boundary — it just
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@@ -391,6 +507,10 @@ class W5100ParallelMaster(Elaboratable):
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rx_rsr = Signal(16)
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rx_rd = Signal(16)
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pkt_len = Signal(16)
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s1_tx_wr = Signal(16) # UDP-socket TX write pointer (send)
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sn_rx_rsr = Signal(16) # UDP-socket RX received size
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sn_rx_rd = Signal(16) # UDP-socket RX read pointer
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sn_pkt_len = Signal(16) # UDP datagram payload length (from header)
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def write_reg(name, addr, payload, nxt, direct=False):
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"""Emit a 2-state block that writes `payload` (a list) to `addr`."""
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@@ -409,6 +529,8 @@ class W5100ParallelMaster(Elaboratable):
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m.next = nxt
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# ── Main control FSM (Phase 1: init only) ────────────────────────────
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if self._enable_udp:
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m.d.sync += self.udp_rx_none.eq(0) # pulse: default low
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with m.FSM(domain="sync", name="main_fsm"):
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with m.State("IDLE"):
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m.d.sync += self.init_done.eq(0)
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@@ -420,6 +542,11 @@ class W5100ParallelMaster(Elaboratable):
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m.next = "RX_CHECK"
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with m.Elif(self.tx_valid & self.tx_sof):
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m.next = "TX_START"
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if self._enable_udp:
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with m.Elif(self.udp_send_req):
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m.next = "UDP_DIPR"
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with m.Elif(self.udp_rx_req):
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m.next = "UDP_RX_RSR"
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# MR = 0x80 software reset (direct A=00), then settle.
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write_reg("MR_RST", _MR, [_MR_RST], "MR_WAIT", direct=True)
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@@ -452,7 +579,21 @@ class W5100ParallelMaster(Elaboratable):
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# Socket 0: MACRAW mode, OPEN, enable interrupt.
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write_reg("S0_MODE", _S0_MR, [_S0_MR_MACRAW], "S0_OPEN")
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write_reg("S0_OPEN", _S0_CR, [_CR_OPEN], "S0_IMR")
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write_reg("S0_IMR", _IMR, [0x01], "INIT_DONE") # enable S0 IRQ
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# After S0 IMR, either finish (plain BBA) or configure the IP stack
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# and open socket 1 in UDP mode (bring-up test build).
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write_reg("S0_IMR", _IMR, [0x01],
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"UDP_CFG_GAR" if self._enable_udp else "INIT_DONE")
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if self._enable_udp:
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# IP stack: gateway, subnet, source IP (SHAR already set above).
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write_reg("UDP_CFG_GAR", _GAR0, self._gateway, "UDP_CFG_SUBR")
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write_reg("UDP_CFG_SUBR", _SUBR0, self._subnet, "UDP_CFG_SIPR")
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write_reg("UDP_CFG_SIPR", _SIPR0, self._src_ip, "UDP_CFG_MR")
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# Socket 1: UDP mode, source port, OPEN, fixed dest port.
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write_reg("UDP_CFG_MR", sn["MR"], [_S1_MR_UDP], "UDP_CFG_PORT")
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write_reg("UDP_CFG_PORT", sn["PORT"], self._src_port, "UDP_CFG_OPEN")
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write_reg("UDP_CFG_OPEN", sn["CR"], [_CR_OPEN], "UDP_CFG_DPORT")
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write_reg("UDP_CFG_DPORT", sn["DPORT"], self._dst_port, "INIT_DONE")
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with m.State("INIT_DONE"):
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m.d.sync += self.init_done.eq(1)
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@@ -581,6 +722,168 @@ class W5100ParallelMaster(Elaboratable):
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write_reg("RX_RECV", _S0_CR, [_CR_RECV], "RX_CLR_IR")
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write_reg("RX_CLR_IR", _S0_IR, [0x04], "IDLE")
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# ── UDP test send (configurable socket) ──────────────────────────
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# Runtime dest IP → Sn_DIPR, read Sn_TX_WR, stream the shell-
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# supplied payload into the socket TX buffer (ring-wrapping),
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# advance Sn_TX_WR, SEND. DPORT + socket open were done at init.
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if self._enable_udp:
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with m.State("UDP_DIPR"): # write Sn_DIPR (runtime, 4 B)
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m.d.sync += self.udp_test_busy.eq(1)
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m.d.sync += [xfer_addr.eq(sn["DIPR"]), xfer_rw.eq(1),
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xfer_stream.eq(0), xfer_sread.eq(0),
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xfer_wrap.eq(0), xfer_direct.eq(0),
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xfer_len.eq(4)]
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m.d.sync += [wbuf[0].eq(self.udp_dst_ip[24:32]),
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wbuf[1].eq(self.udp_dst_ip[16:24]),
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wbuf[2].eq(self.udp_dst_ip[8:16]),
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wbuf[3].eq(self.udp_dst_ip[0:8])]
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m.d.sync += xfer_start.eq(1)
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m.next = "UDP_DIPR_W"
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with m.State("UDP_DIPR_W"):
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m.d.sync += xfer_start.eq(0)
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with m.If(xfer_done):
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m.next = "UDP_TXWR"
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with m.State("UDP_TXWR"): # read Sn_TX_WR (2 B)
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m.d.sync += [xfer_addr.eq(sn["TX_WR"]), xfer_rw.eq(0),
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xfer_stream.eq(0), xfer_sread.eq(0),
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xfer_wrap.eq(0), xfer_direct.eq(0),
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xfer_len.eq(2)]
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m.d.sync += xfer_start.eq(1)
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m.next = "UDP_TXWR_W"
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with m.State("UDP_TXWR_W"):
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m.d.sync += xfer_start.eq(0)
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with m.If(xfer_done):
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m.d.sync += s1_tx_wr.eq(Cat(rbuf[1], rbuf[0]))
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m.next = "UDP_DATA"
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with m.State("UDP_DATA"): # stream payload → Sn TX buffer
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m.d.sync += [xfer_addr.eq(sn["TX_BASE"] + (s1_tx_wr & _SN_MASK)),
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xfer_rw.eq(1), xfer_stream.eq(1),
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xfer_sread.eq(0), xfer_direct.eq(0),
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xfer_wrap.eq(1), xfer_wbase.eq(sn["TX_BASE"]),
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xfer_wend.eq(sn["TX_BASE"] + _SN_MASK + 1),
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udp_streaming.eq(1)]
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m.d.sync += xfer_start.eq(1)
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m.next = "UDP_DATA_W"
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with m.State("UDP_DATA_W"):
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m.d.sync += xfer_start.eq(0)
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with m.If(xfer_done):
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m.d.sync += [xfer_stream.eq(0), xfer_wrap.eq(0),
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udp_streaming.eq(0),
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s1_tx_wr.eq(s1_tx_wr + s_count)]
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m.next = "UDP_UPDPTR"
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with m.State("UDP_UPDPTR"): # write back Sn_TX_WR (2 B)
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m.d.sync += [xfer_addr.eq(sn["TX_WR"]), xfer_rw.eq(1),
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xfer_stream.eq(0), xfer_sread.eq(0),
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xfer_wrap.eq(0), xfer_direct.eq(0),
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xfer_len.eq(2)]
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m.d.sync += [wbuf[0].eq(s1_tx_wr[8:16]),
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wbuf[1].eq(s1_tx_wr[0:8])]
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m.d.sync += xfer_start.eq(1)
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m.next = "UDP_UPDPTR_W"
|
||||
with m.State("UDP_UPDPTR_W"):
|
||||
m.d.sync += xfer_start.eq(0)
|
||||
with m.If(xfer_done):
|
||||
m.next = "UDP_SEND"
|
||||
|
||||
write_reg("UDP_SEND", sn["CR"], [_CR_SEND], "UDP_DONE")
|
||||
with m.State("UDP_DONE"):
|
||||
m.d.sync += self.udp_test_busy.eq(0)
|
||||
m.next = "IDLE"
|
||||
|
||||
# ── UDP test receive (configurable socket) ───────────────────────
|
||||
# Poll-driven (the shell pulses udp_rx_req). Read Sn_RX_RSR; if 0,
|
||||
# pulse udp_rx_none. Otherwise read Sn_RX_RD, read the 8-byte WIZnet
|
||||
# UDP header ([srcIP 4][srcPort 2][len 2]), stream `len` payload
|
||||
# bytes out on udp_rx_* (ring-wrapping), advance Sn_RX_RD by 8+len,
|
||||
# RECV, clear the socket IR. MACRAW socket-0 RX is untouched.
|
||||
if self._enable_udp:
|
||||
with m.State("UDP_RX_RSR"): # read Sn_RX_RSR (2 B)
|
||||
m.d.sync += self.udp_rx_busy.eq(1)
|
||||
m.d.sync += [xfer_addr.eq(sn["RX_RSR"]), xfer_rw.eq(0),
|
||||
xfer_stream.eq(0), xfer_sread.eq(0),
|
||||
xfer_wrap.eq(0), xfer_direct.eq(0),
|
||||
xfer_len.eq(2)]
|
||||
m.d.sync += xfer_start.eq(1)
|
||||
m.next = "UDP_RX_RSR_W"
|
||||
with m.State("UDP_RX_RSR_W"):
|
||||
m.d.sync += xfer_start.eq(0)
|
||||
with m.If(xfer_done):
|
||||
m.d.sync += sn_rx_rsr.eq(Cat(rbuf[1], rbuf[0]))
|
||||
m.next = "UDP_RX_CHK"
|
||||
with m.State("UDP_RX_CHK"):
|
||||
with m.If(sn_rx_rsr == 0):
|
||||
m.d.sync += [self.udp_rx_none.eq(1),
|
||||
self.udp_rx_busy.eq(0)]
|
||||
m.next = "IDLE"
|
||||
with m.Else():
|
||||
m.next = "UDP_RX_RD"
|
||||
|
||||
with m.State("UDP_RX_RD"): # read Sn_RX_RD (2 B)
|
||||
m.d.sync += [xfer_addr.eq(sn["RX_RD"]), xfer_rw.eq(0),
|
||||
xfer_stream.eq(0), xfer_sread.eq(0),
|
||||
xfer_wrap.eq(0), xfer_direct.eq(0),
|
||||
xfer_len.eq(2)]
|
||||
m.d.sync += xfer_start.eq(1)
|
||||
m.next = "UDP_RX_RD_W"
|
||||
with m.State("UDP_RX_RD_W"):
|
||||
m.d.sync += xfer_start.eq(0)
|
||||
with m.If(xfer_done):
|
||||
m.d.sync += sn_rx_rd.eq(Cat(rbuf[1], rbuf[0]))
|
||||
m.next = "UDP_RX_HDR"
|
||||
|
||||
with m.State("UDP_RX_HDR"): # read 8-byte UDP header (wrap)
|
||||
m.d.sync += [xfer_addr.eq(sn["RX_BASE"] + (sn_rx_rd & _SN_MASK)),
|
||||
xfer_rw.eq(0), xfer_stream.eq(0), xfer_sread.eq(0),
|
||||
xfer_direct.eq(0), xfer_len.eq(8), xfer_wrap.eq(1),
|
||||
xfer_wbase.eq(sn["RX_BASE"]),
|
||||
xfer_wend.eq(sn["RX_BASE"] + _SN_MASK + 1)]
|
||||
m.d.sync += xfer_start.eq(1)
|
||||
m.next = "UDP_RX_HDR_W"
|
||||
with m.State("UDP_RX_HDR_W"):
|
||||
m.d.sync += xfer_start.eq(0)
|
||||
with m.If(xfer_done):
|
||||
# header[6:8] = payload length (big-endian)
|
||||
m.d.sync += sn_pkt_len.eq(Cat(rbuf[7], rbuf[6]))
|
||||
m.next = "UDP_RX_FRAME"
|
||||
|
||||
with m.State("UDP_RX_FRAME"): # stream `len` payload bytes out
|
||||
m.d.sync += [xfer_addr.eq(sn["RX_BASE"] + ((sn_rx_rd + 8) & _SN_MASK)),
|
||||
xfer_rw.eq(0), xfer_stream.eq(0), xfer_sread.eq(1),
|
||||
xfer_direct.eq(0), xfer_rcount.eq(sn_pkt_len),
|
||||
xfer_wrap.eq(1), xfer_wbase.eq(sn["RX_BASE"]),
|
||||
xfer_wend.eq(sn["RX_BASE"] + _SN_MASK + 1),
|
||||
udp_rx_streaming.eq(1)]
|
||||
m.d.sync += xfer_start.eq(1)
|
||||
m.next = "UDP_RX_FRAME_W"
|
||||
with m.State("UDP_RX_FRAME_W"):
|
||||
m.d.sync += xfer_start.eq(0)
|
||||
with m.If(xfer_done):
|
||||
m.d.sync += [xfer_sread.eq(0), xfer_wrap.eq(0),
|
||||
udp_rx_streaming.eq(0)]
|
||||
m.next = "UDP_RX_UPDRD"
|
||||
|
||||
with m.State("UDP_RX_UPDRD"): # Sn_RX_RD += 8 + len, write back
|
||||
m.d.sync += [xfer_addr.eq(sn["RX_RD"]), xfer_rw.eq(1),
|
||||
xfer_stream.eq(0), xfer_sread.eq(0),
|
||||
xfer_wrap.eq(0), xfer_direct.eq(0), xfer_len.eq(2)]
|
||||
m.d.sync += [wbuf[0].eq((sn_rx_rd + 8 + sn_pkt_len)[8:16]),
|
||||
wbuf[1].eq((sn_rx_rd + 8 + sn_pkt_len)[0:8])]
|
||||
m.d.sync += xfer_start.eq(1)
|
||||
m.next = "UDP_RX_UPDRD_W"
|
||||
with m.State("UDP_RX_UPDRD_W"):
|
||||
m.d.sync += xfer_start.eq(0)
|
||||
with m.If(xfer_done):
|
||||
m.next = "UDP_RX_RECV"
|
||||
|
||||
write_reg("UDP_RX_RECV", sn["CR"], [_CR_RECV], "UDP_RX_CLR_IR")
|
||||
write_reg("UDP_RX_CLR_IR", sn["IR"], [0x04], "UDP_RX_DONE")
|
||||
with m.State("UDP_RX_DONE"):
|
||||
m.d.sync += self.udp_rx_busy.eq(0)
|
||||
m.next = "IDLE"
|
||||
|
||||
return m
|
||||
|
||||
|
||||
@@ -831,6 +1134,217 @@ if __name__ == "__main__":
|
||||
|
||||
sim.run()
|
||||
|
||||
# ── UDP-test path (configurable socket, enable_udp_test=True) ───────────
|
||||
# Reuses the same address-agnostic bus model (it reads/writes model_mem at
|
||||
# whatever IDM_AR is set), so it transparently covers the IP-config and
|
||||
# socket registers. Verifies: init programs GAR/SUBR/SIPR + opens the
|
||||
# socket in UDP mode; a udp_send_req writes Sn_DIPR to the runtime dest,
|
||||
# streams the payload into the socket TX buffer, advances Sn_TX_WR, issues
|
||||
# SEND; and a udp_rx_req reads a datagram (header + payload) back out.
|
||||
SRC_IP, SUBNET, GATEWAY = "10.0.0.7", "255.255.255.0", "10.0.0.1"
|
||||
DEF_DST, DST_PORT, SRC_PORT = "192.168.1.100", 6464, 40000
|
||||
UDP_SOCK = 3
|
||||
S = _socket_addrs(UDP_SOCK)
|
||||
dut2 = W5100ParallelMaster(
|
||||
strobe_cycles=3, reset_cycles=10, enable_udp_test=True,
|
||||
udp_socket=UDP_SOCK, src_ip=SRC_IP, subnet=SUBNET, gateway=GATEWAY,
|
||||
dst_ip=DEF_DST, src_port=SRC_PORT, dst_port=DST_PORT)
|
||||
|
||||
writes2, model_mem2 = [], {}
|
||||
|
||||
async def w5100_model2(ctx):
|
||||
idm_ar = 0
|
||||
mr = 0
|
||||
prev_wr = prev_rd = 1
|
||||
async for vals in ctx.tick("sync").sample(
|
||||
dut2.cs_n, dut2.rd_n, dut2.wr_n,
|
||||
dut2.bus_addr, dut2.bus_data_o):
|
||||
cs, rd, wr, a, do = vals[-5:]
|
||||
ai = (mr >> 1) & 1
|
||||
if cs == 0 and rd == 0:
|
||||
if a == _A_MR: val = mr
|
||||
elif a == _A_AR0: val = (idm_ar >> 8) & 0xFF
|
||||
elif a == _A_AR1: val = idm_ar & 0xFF
|
||||
else: val = model_mem2.get(idm_ar, 0)
|
||||
ctx.set(dut2.bus_data_i, val)
|
||||
if cs == 0 and prev_wr == 0 and wr == 1:
|
||||
if a == _A_MR:
|
||||
mr = do; writes2.append(("MR", do))
|
||||
elif a == _A_AR0: idm_ar = (idm_ar & 0x00FF) | (do << 8)
|
||||
elif a == _A_AR1: idm_ar = (idm_ar & 0xFF00) | do
|
||||
else:
|
||||
model_mem2[idm_ar] = do; writes2.append((idm_ar, do))
|
||||
if ai: idm_ar = (idm_ar + 1) & 0xFFFF
|
||||
if cs == 0 and prev_rd == 0 and rd == 1 and a == _A_DR and ai:
|
||||
idm_ar = (idm_ar + 1) & 0xFFFF
|
||||
prev_wr, prev_rd = wr, rd
|
||||
|
||||
def _u16(addr):
|
||||
return (model_mem2.get(addr, 0) << 8) | model_mem2.get(addr + 1, 0)
|
||||
|
||||
async def testbench2(ctx):
|
||||
ctx.set(dut2.par, PAR)
|
||||
ctx.set(dut2.udp_pl_valid, 0)
|
||||
await ctx.tick("sync").repeat(2)
|
||||
|
||||
# U1: init → IP stack + socket-1 UDP open.
|
||||
ctx.set(dut2.init_req, 1)
|
||||
await ctx.tick("sync").repeat(1)
|
||||
ctx.set(dut2.init_req, 0)
|
||||
done = False
|
||||
for _ in range(6000):
|
||||
await ctx.tick("sync").repeat(1)
|
||||
if ctx.get(dut2.init_done):
|
||||
done = True; break
|
||||
if not done:
|
||||
errors.append("UDP: init_done never asserted")
|
||||
|
||||
checks = {
|
||||
_GAR0: _ip_bytes(GATEWAY), _SUBR0: _ip_bytes(SUBNET),
|
||||
_SIPR0: _ip_bytes(SRC_IP),
|
||||
}
|
||||
for base, octets in checks.items():
|
||||
got = [model_mem2.get(base + i) for i in range(4)]
|
||||
if got != octets:
|
||||
errors.append(f"UDP init {base:#06x}: got {got}, want {octets}")
|
||||
if model_mem2.get(S["MR"]) != _S1_MR_UDP:
|
||||
errors.append(f"UDP init Sn_MR: got {model_mem2.get(S['MR'])}, want UDP")
|
||||
if _u16(S["PORT"]) != SRC_PORT:
|
||||
errors.append(f"UDP init Sn_PORT: {_u16(S['PORT'])} != {SRC_PORT}")
|
||||
if _u16(S["DPORT"]) != DST_PORT:
|
||||
errors.append(f"UDP init Sn_DPORT: {_u16(S['DPORT'])} != {DST_PORT}")
|
||||
if (S["CR"], _CR_OPEN) not in writes2:
|
||||
errors.append("UDP init: socket OPEN not issued")
|
||||
print(f"U1 init (socket {UDP_SOCK}): GAR/SUBR/SIPR set, Sn_MR=UDP, "
|
||||
f"Sn_PORT={_u16(S['PORT'])} Sn_DPORT={_u16(S['DPORT'])} OPEN issued")
|
||||
|
||||
# U2: send one datagram to a runtime dest IP with a payload.
|
||||
DST = "192.168.1.55"
|
||||
PAYLOAD = list(b"HELLO-ETH")
|
||||
ctx.set(dut2.udp_dst_ip, int.from_bytes(bytes(_ip_bytes(DST)), "big"))
|
||||
idx = 0
|
||||
ctx.set(dut2.udp_pl_data, PAYLOAD[0])
|
||||
ctx.set(dut2.udp_pl_last, 1 if len(PAYLOAD) == 1 else 0)
|
||||
ctx.set(dut2.udp_pl_valid, 1)
|
||||
ctx.set(dut2.udp_send_req, 1)
|
||||
await ctx.tick("sync").repeat(1)
|
||||
ctx.set(dut2.udp_send_req, 0)
|
||||
sent = False
|
||||
for _ in range(4000):
|
||||
await ctx.tick("sync").repeat(1)
|
||||
if ctx.get(dut2.udp_pl_ready) and ctx.get(dut2.udp_pl_valid):
|
||||
idx += 1
|
||||
if idx < len(PAYLOAD):
|
||||
ctx.set(dut2.udp_pl_data, PAYLOAD[idx])
|
||||
ctx.set(dut2.udp_pl_last, 1 if idx == len(PAYLOAD) - 1 else 0)
|
||||
else:
|
||||
ctx.set(dut2.udp_pl_valid, 0)
|
||||
if model_mem2.get(S["CR"]) == _CR_SEND:
|
||||
sent = True; break
|
||||
ctx.set(dut2.udp_pl_valid, 0)
|
||||
if not sent:
|
||||
errors.append("UDP send: SEND command never issued")
|
||||
for _ in range(50):
|
||||
await ctx.tick("sync").repeat(1)
|
||||
if ctx.get(dut2.udp_test_busy) == 0:
|
||||
break
|
||||
|
||||
dip = [model_mem2.get(S["DIPR"] + i) for i in range(4)]
|
||||
if dip != _ip_bytes(DST):
|
||||
errors.append(f"UDP send DIPR: got {dip}, want {_ip_bytes(DST)}")
|
||||
buf = [model_mem2.get(S["TX_BASE"] + i) for i in range(len(PAYLOAD))]
|
||||
if buf != PAYLOAD:
|
||||
errors.append(f"UDP send payload: {buf} != {PAYLOAD}")
|
||||
if _u16(S["TX_WR"]) != len(PAYLOAD):
|
||||
errors.append(f"UDP send Sn_TX_WR: {_u16(S['TX_WR'])} != {len(PAYLOAD)}")
|
||||
print(f"U2 send: DIPR={dip} payload={bytes(buf)!r} "
|
||||
f"Sn_TX_WR={_u16(S['TX_WR'])} SEND={sent}")
|
||||
|
||||
# ── U3: receive a UDP datagram from the socket RX buffer ─────────────
|
||||
# WIZnet UDP RX format: [srcIP(4)][srcPort(2)][len(2)][payload].
|
||||
model_mem2[S["CR"]] = 0x00
|
||||
SRC = _ip_bytes("192.168.1.9")
|
||||
SPORT = 6464
|
||||
RPAYLOAD = list(b"WORLD!")
|
||||
rlen = len(RPAYLOAD)
|
||||
rx_rd0 = 0x0000
|
||||
hdr = SRC + [SPORT >> 8, SPORT & 0xFF, (rlen >> 8) & 0xFF, rlen & 0xFF]
|
||||
packet = hdr + RPAYLOAD
|
||||
for i, b in enumerate(packet):
|
||||
model_mem2[S["RX_BASE"] + ((rx_rd0 + i) & _SN_MASK)] = b
|
||||
total = len(packet)
|
||||
model_mem2[S["RX_RSR"]] = (total >> 8) & 0xFF
|
||||
model_mem2[S["RX_RSR"] + 1] = total & 0xFF
|
||||
model_mem2[S["RX_RD"]] = (rx_rd0 >> 8) & 0xFF
|
||||
model_mem2[S["RX_RD"] + 1] = rx_rd0 & 0xFF
|
||||
|
||||
ctx.set(dut2.udp_rx_ready, 1)
|
||||
rx_got = []
|
||||
got_none = [False]
|
||||
ctx.set(dut2.udp_rx_req, 1)
|
||||
# hold req until the master goes busy, then drop it
|
||||
for _ in range(200):
|
||||
await ctx.tick("sync").repeat(1)
|
||||
if ctx.get(dut2.udp_rx_busy):
|
||||
ctx.set(dut2.udp_rx_req, 0); break
|
||||
recvd = False
|
||||
for _ in range(3000):
|
||||
await ctx.tick("sync").repeat(1)
|
||||
if ctx.get(dut2.udp_rx_valid) and ctx.get(dut2.udp_rx_ready):
|
||||
rx_got.append(ctx.get(dut2.udp_rx_data))
|
||||
if ctx.get(dut2.udp_rx_none):
|
||||
got_none[0] = True
|
||||
if model_mem2.get(S["CR"]) == _CR_RECV:
|
||||
recvd = True; break
|
||||
for _ in range(30):
|
||||
await ctx.tick("sync").repeat(1)
|
||||
ctx.set(dut2.udp_rx_ready, 0)
|
||||
|
||||
if rx_got != RPAYLOAD:
|
||||
errors.append(f"U3 RX payload: {bytes(rx_got)!r} != {bytes(RPAYLOAD)!r}")
|
||||
new_rd = _u16(S["RX_RD"])
|
||||
if new_rd != rx_rd0 + total:
|
||||
errors.append(f"U3 RX_RD advance: got {new_rd}, want {rx_rd0 + total}")
|
||||
if model_mem2.get(S["CR"]) != _CR_RECV:
|
||||
errors.append("U3 RX: RECV command not issued")
|
||||
if got_none[0]:
|
||||
errors.append("U3 RX: udp_rx_none pulsed despite data present")
|
||||
print(f"U3 recv: payload={bytes(rx_got)!r} RX_RD={new_rd} "
|
||||
f"RECV={model_mem2.get(S['CR'])==_CR_RECV}")
|
||||
|
||||
# ── U4: RX poll with an empty buffer → udp_rx_none, no stream ────────
|
||||
model_mem2[S["RX_RSR"]] = 0
|
||||
model_mem2[S["RX_RSR"] + 1] = 0
|
||||
model_mem2[S["CR"]] = 0x00
|
||||
none_seen = False
|
||||
streamed = False
|
||||
ctx.set(dut2.udp_rx_req, 1)
|
||||
for _ in range(200):
|
||||
await ctx.tick("sync").repeat(1)
|
||||
if ctx.get(dut2.udp_rx_busy):
|
||||
ctx.set(dut2.udp_rx_req, 0); break
|
||||
for _ in range(200):
|
||||
await ctx.tick("sync").repeat(1)
|
||||
if ctx.get(dut2.udp_rx_none):
|
||||
none_seen = True
|
||||
if ctx.get(dut2.udp_rx_valid):
|
||||
streamed = True
|
||||
if none_seen and not ctx.get(dut2.udp_rx_busy):
|
||||
break
|
||||
if not none_seen:
|
||||
errors.append("U4 RX-empty: udp_rx_none never pulsed")
|
||||
if streamed:
|
||||
errors.append("U4 RX-empty: streamed data despite empty buffer")
|
||||
if model_mem2.get(S["CR"]) == _CR_RECV:
|
||||
errors.append("U4 RX-empty: RECV issued on empty buffer")
|
||||
print(f"U4 recv-empty: none={none_seen} streamed={streamed}")
|
||||
|
||||
sim2 = Simulator(dut2)
|
||||
sim2.add_clock(Period(MHz=24), domain="sync")
|
||||
sim2.add_testbench(testbench2)
|
||||
sim2.add_process(w5100_model2)
|
||||
sim2.run()
|
||||
|
||||
if errors:
|
||||
print("\nFAILURES:")
|
||||
for e in errors:
|
||||
|
||||
Reference in New Issue
Block a user