fix(efuse): connect U13's exposed thermal pad to GND

The TPS25961's exposed pad is GND and the datasheet requires it be connected
to the GND plane (Table 5-1; package note 3 adds a mechanical requirement).
REVIEW.md claimed this was honoured because the footprint is the _ThermalVias
variant -- but the variant alone connects nothing.  hardware/TPS25961.kicad_sym
defined pins 1-6 only, with no pin for the exposed pad, so KiCad had nothing to
map onto footprint pad 7 and left it netless: an isolated copper island under
the chip with its thermal vias going nowhere.

Adds pin 7 (GND, power_in, hidden, stacked on pin 4) to the symbol library, the
cached symbol in exi.kicad_sch, and the U13 instance.

PCB updated and verified: U13 pad 7 carries GND on all four elements (both SMD
rects and both thermal vias), R48 placed, EFUSE_OVLO routed, R49 gone.  DRC
reports 0 violations, 0 unconnected pads and 0 schematic parity issues -- the
0-unconnected result is what confirms pad 7 is tied into the GND network rather
than merely labelled.  The 4 DRC errors previously dismissed as zone-fill
phantoms on this pad are gone, though zones were refilled in the same pass so
that is not proof of cause either way.

Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>

hardware/re-bba-rb/TODO.md

@@ -261,7 +261,13 @@ schematic changes.
       Verified after the edit: nets are 12V_RAW(R46.2) / EFUSE_EN(R46.1, R47.1,
       U13.5) / EFUSE_OVLO(R47.2, R48.1, U13.2) / GND(R48.2, R45.2, U13.4);
       component count 150 -> 151 with nothing dropped; ERC 0 violations.
-      **PCB TODO:** place R48 near U13, route the new EFUSE_OVLO net, and
+      **Also fixed 2026-10-02:** U13's exposed thermal pad had NO NET — the
+      custom symbol defined pins 1–6 only, so footprint pad 7 was an isolated
+      island despite the `_ThermalVias` footprint. Added pin 7 (GND, hidden,
+      stacked on pin 4); datasheet says the pad *"must be connected to GND
+      plane"*.
+      **PCB DONE 2026-10-02** — R48 placed, EFUSE_OVLO routed, pad 7 on GND
+      (all 4 elements), DRC 0 errors / 0 unconnected / 0 parity. Remaining:
       re-export BOM + CPL (reapplying CPL_ROTATIONS.md afterwards).
       Gives **UVLO 6.78 V** and **OVLO 15.18 V typ (14.47–15.78 worst case)**
       — under U3's 17 V input rating, which is what actually caps the OVLO