From d156df1dda91b71e4980c82c037ab111723b30f5 Mon Sep 17 00:00:00 2001 From: Dennis Brentjes Date: Wed, 30 Sep 2026 18:53:36 +0000 Subject: [PATCH] docs: record post-fix timing sweep (2/8 seeds, best 60.03 MHz) Co-Authored-By: Claude Opus 5 --- CLAUDE.md | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/CLAUDE.md b/CLAUDE.md index 87430dc..8e74177 100644 --- a/CLAUDE.md +++ b/CLAUDE.md @@ -331,7 +331,16 @@ Two bring-up gotchas, both cost real debugging time: until CS (the DMA path). `hardware/re-bba-rb/exi_regcheck_rpi.py` clocks correctly and is the reference host-side probe. -**Measured 2026-09-30**, `EXI_J4=1` + socket-3 UDP, `--seeds 8`: +**Measured 2026-09-30 AFTER the TWD TX fix**, `EXI_J4=1` + socket-3 UDP, +`--seeds 8`: `clk` 28.1–30.2 MHz (PASS on all 8); `capture_clk` **2 of 8 PASS** +(seeds 4, 7), best **seed 7 = 60.03 MHz** (+6.0 MHz / 11% margin). The fix's +handful of extra exi-domain cells (`twd_armed`/`tx_queued`) dropped the pass +rate from 4/8 to 2/8 even though none of that logic is in the capture domain — +added cells raise congestion and capture is routing-bound. Best seed is +comfortably usable; just sweep and flash the winner. Earlier figures, before +the fix: + +**Measured 2026-09-30 (pre-fix)**, `EXI_J4=1` + socket-3 UDP, `--seeds 8`: `clk` 29.2–31.4 MHz (PASS on all 8); `capture_clk` **4 of 8 PASS** (seeds 2, 5, 6, 8), best **seed 8 = 63.09 MHz** (+9.1 MHz / 17% margin). Same pass rate as the default build and a better best seed, so the merge costs no measurable