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Fix EXI DO/DI swap: rename nets + swap damping resistors, no copper changes

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SP1 DO/DI naming is console-perspective (verified against SD Gecko and
SD2SP2 wiring): pin 6 DO = GC data out = adapter MOSI input, pin 9 DI =
GC data in = adapter MISO output. The design doc's SP1 table had the
roles reversed and the schematic followed it, putting the FPGA's MISO
driver on the GC-driven DO line (bus contention).

Fix keeps all PCB routing identical:
- Swap net names EXI_MOSI(_RAW) <-> EXI_MISO(_RAW) across exi/Fpga/root
  sheets and the PCB (also renames the D2 PUSB3AB6 channel assignments).
- Swap R21 (22R) <-> R25 (33R) identities between the two footprint
  positions so 33R stays on the FPGA-driven MISO line, 22R on the MOSI
  input.
- Correct the SP1 pin table + MISO-tristate note in
  docs/gc_bba_fpga_design.md (root cause).

Resulting board pin map (for the future board PCF): EXI_MOSI = FPGA
pin 4 (IOB_8a, input), EXI_MISO = pin 3 (IOB_9b, output).

Verified: ERC 0, DRC 0 errors with schematic parity 0, netlist shows
J3.6(DO)->R21->pin 4 and J3.9(DI)->R25->pin 3.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
This commit is contained in:
Dennis Brentjes
2026-07-18 12:36:41 +00:00
parent 4704dfbb36
commit fe96876a80
7 changed files with 94 additions and 86 deletions
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CLAUDE.md
+5 -5
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@@ -256,11 +256,11 @@ before ordering the interposer PCB; not part of the FPGA build.
`hardware/re-bba-rb/` — the actual adapter PCB (FT2232H + iCE40UP5K + W5100S,
powered from SP1 12 V via buck). **Open findings from the 2026-07-17 hardware
review live in `hardware/re-bba-rb/TODO.md`** — read it before editing the
schematics, ordering boards, or writing the board PCF. Highlights: EXI DO/DI are
swapped vs the (incorrect) SP1 table in `docs/gc_bba_fpga_design.md` (DO = GC→
adapter = MOSI); the W5100S MDI 49.9 Ω termination network is missing; the FTDI
EEPROM needs its 2.2 k/10 k resistors; stock iceprog doesn't match the FTDI pin
mapping.
schematics, ordering boards, or writing the board PCF. Highlights: the W5100S
MDI 49.9 Ω termination network is missing; the FTDI EEPROM needs its 2.2 k/10 k
resistors; stock iceprog doesn't match the FTDI pin mapping. (The EXI DO/DI
swap found in the review is FIXED — SP1 naming is console-perspective, DO = GC→
adapter = MOSI; board pin map: EXI_MOSI = FPGA pin 4, EXI_MISO = pin 3.)
---